ADC reconfiguration for different data rates

A method of a receiver that includes a clock generator and a plurality of time-interleaved analog-to-digital converters (ADC) comprising a plurality of sub-ADCs, the method comprising:

• generating a plurality of sampling clock signals having a plurality of sampling phases using circuitry of the clock generator, each of the plurality of sampling clock signals having a corresponding one of the plurality of sampling phases;
• sampling an analog input signal using each of the plurality of sub-ADCs, the analog input signal sampled by each of the plurality of sub-ADCs at one of the plurality of sampling phases that corresponds to the sub-ADC to convert the sampled analog input signal into a digital sample;
• wherein responsive to the receiver being configured to operate at a first data rate, enabling a first set of the plurality of sub-ADCs of at least one of the plurality of time-interleaved ADCs and a first portion of the circuitry of the clock generator to sample the analog input signal at the first data rate;
• and
• wherein responsive to the receiver being configured to operate at a second data rate that is different from the first data rate, enabling a second set of the plurality of sub-ADCs of the at least one of the plurality of time-interleaved ADCs and a second portion of the circuitry of the clock generator to sample the analog input signal at the second data rate, the second set of the plurality of sub-ADCs including sub-ADCs that are different from the sub-ADCs from the first set, and the second portion of the circuitry different from the first portion of the circuitry.

A receiver comprising:

• a clock generator including circuitry that generates a plurality of sampling clock signals having a plurality of sampling phases, each of the plurality of sampling clock signals having a corresponding one of the plurality of sampling phases, the circuitry of the clock generator including:
• a plurality of phase interpolators that receive a reference clock signal, each phase interpolator generating a plurality of clock signals based on the reference clock signal, wherein each of the plurality of clock signals have a different sampling phase;
• a plurality of clock dividers, each of the plurality of clock dividers receiving the plurality of clock signals from a corresponding one of the plurality of phase interpolators and generating a portion of the plurality of sampling clock signals having the plurality of sampling phases of the clock generator;
• and
• a plurality of time-interleaved analog-to-digital converters (ADC), each of the plurality of time-interleaved ADCs including a plurality of sub-ADCs that sample an analog input signal, wherein each of the plurality of sub-ADCs sample the analog input signal at one of the plurality of sampling phases that corresponds to the sub-ADC to convert the sampled analog input signal into a digital sample;
• wherein responsive to the receiver being configured to operate at a first data rate, a first set of the plurality of sub-ADCs of at least one of the plurality of time-interleaved ADCs and a first portion of the circuitry of the clock generator are enabled to sample the analog input signal;
• and
• wherein responsive to the receiver being configured to operate at a second data rate that is different from the first data rate, a second set of the plurality of sub-ADCs of the at least one of the plurality of time-interleaved ADCs and a second portion of the circuitry of the clock generator are enabled to sample the analog input signal, the second set of the plurality of sub-ADCs including sub-ADCs that are different from the sub-ADCs from the first set, and the second portion of the circuitry different from the first portion of the circuitry.