Adiabatic logic cell
AssigneeCommissariat A L'energie Atomique Et Aux Energies Alternatives
InventorsGaël Pillonnet, Hervé Fanet
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Abstract
An adiabatic logic cell including a first MOS transistor coupling a node for applying a periodic variable supply voltage of the cell to a floating node for providing an output logic signal of the cell, wherein the first transistor is a dual-gate transistor including a front gate coupled to a node for applying an input logic signal of the cell, and a back gate coupled to a node for applying a first periodic variable bias voltage.
Claims17
An adiabatic logic cell comprising a first MOS transistor coupling a node for applying a periodic variable supply voltage of the cell to a floating node for providing an output logic signal of the cell, wherein the first MOS transistor is a dual-gate transistor comprising a front gate coupled to a node for applying an input logic signal of the cell, and a back gate coupled to a node for applying a first periodic variable bias voltage, wherein the periodic variable bias voltage and the periodic variable supply voltage have substantially the same frequency and the same form.
An adiabatic logic cell comprising a first MOS transistor coupling a node for applying a periodic variable supply voltage of the cell to a floating node for providing an output logic signal of the cell, wherein the first MOS transistor is a dual-gate transistor comprising a front gate coupled to a node for applying an input logic signal of the cell, and a back gate coupled to a node for applying a first periodic variable bias voltage, wherein the periodic variable bias voltage is chosen so that the first MOS transistor has a threshold voltage that varies in a periodic manner, substantially at the same frequency as the periodic variable supply voltage, and has a maximum value when the periodic variable supply voltage has a maximum value, and a minimum value when the periodic variable supply voltage has a minimum value.
Dependencies are inferred from the claim text.