Back to results
US 10,719,236 B2Granted
Memory controller with non-volatile buffer for persistent memory operations
AssigneeArm Limited
InventorsAndreas Hansson, Stephan Diestelhorst, Wei Wang, Irenéus Johannes de Jong
Life of this patent
Estimating the term…
Abstract
Subject matter disclosed herein may relate to buffers, and may relate more particularly to non-volatile buffers for memory operations.
Claims19
An apparatus, comprising:
- a processor;
- and
- a memory controller located on a particular integrated circuit die with the processor, wherein the memory controller to include a non-volatile buffer comprising one or more correlated electron switch devices, wherein the memory controller to interface with a separate non-volatile memory device, wherein the memory controller to store in the non-volatile buffer of the memory controller one or more signals and/or states associated with a persistent memory operation to be directed to the separate non-volatile memory device, the signals and/or states associated with the persistent memory operation to be received from the processor,
- wherein to store the one or more signals and/or states to comprise the signals and/or states associated with the persistent memory operation, a circuit to apply a particular current signal to at least one of the one or more correlated electron switch devices during an operation to place the at least one of the one or more correlated electron switch devices in a first impedance state and to establish a reset condition current density requirement for a subsequent operation to place the at least one of the one or more correlated electron switch devices in a second impedance state, the memory controller further to signal to the processor completion of the persistent memory operation responsive to storage of the signals and/or states associated with the persistent memory operation in the non-volatile buffer.
1 more element
A method, comprising:
- storing, in non-volatile buffer of a memory controller, one or more signals and/or states associated with a persistent memory operation communicated between a processor and the memory controller, wherein the processor and the memory controller are located on a particular integrated circuit die, wherein the signals and/or states associated with the persistent memory operation are directed to a separate non-volatile memory device, wherein the non-volatile buffer comprises one or more correlated electron switch devices, and wherein the storing the one or more signals and/or states associated with the persistent memory operation in the non-volatile buffer includes applying a particular current signal to at least one of the one or more correlated electron switch devices during an operation to place the at least one of the one or more correlated electron switch devices in a first impedance state and to establish a reset condition current density requirement for a subsequent operation to place the at least one of the one or more correlated electron switch devices in a second impedance state;
- and
- communicating between the memory controller and the processor a message indicating completion of the persistent memory operation responsive to the storing the one or more signals and/or states associated with the persistent memory operation in the non-volatile buffer.
A system, comprising:
- a non-volatile memory device;
- a processor and a memory controller located on a particular integrated circuit die, wherein the processor to execute a persistent memory operation directed to a memory location in the non-volatile memory device;
- and
- wherein the memory controller to receive one or more signals and/or states associated with the persistent memory operation from the processor, wherein the memory controller to store in one or more correlated electron switch devices of a non-volatile buffer of the memory controller the signals and/or states associated with the persistent memory operation, wherein to store the one or more signals and/or states associated with the persistent memory operation, a circuit to apply a particular current signal to at least one of the one or more correlated electron switch devices during an operation to place the at least one of the one or more correlated electron switch devices in a first impedance state and to establish a reset condition current density requirement for a subsequent operation to place the at least one of the one or more correlated electron switch devices in a second impedance state, the memory controller further to signal to the processor completion of the persistent memory operation responsive to storage of the signals and/or states associated with the persistent memory operation in the non-volatile buffer.
1 more element
Dependencies are inferred from the claim text.