Inductor-less divide-by-3 injection locked frequency divider

A frequency divider configured to frequency-divide an input signal to generate a frequency-divided output signal, the frequency divider comprising:

• a ring oscillator including a plurality of delay stages;
• a first coupling circuit configured to inject the input signal into a first delay stage of the plurality of delay stages based on a first retiming signal;
• and
• first logic configured to generate the first retiming signal based on a logical combination of the input signal and an oscillation waveform appearing at a second delay stage of the plurality of delay stages, and further configured to sequentially alternate between triggering the injection of the input signal into the first delay stage based on rising edges of the input signal and triggering the injection of the input signal into the first delay stage based on falling edges of the input signal.

A method for frequency-dividing an input signal to generate a frequency-divided output signal, the method comprising:

• generating, in an oscillator including a plurality of delay stages, an oscillation waveform having a frequency equal to a frequency of the frequency-divided output signal;
• generating a first retiming signal based on a logical combination of the input signal and the oscillation waveform appearing at a selected delay stage of the oscillator;
• and
• injecting the input signal into a previous delay stage of the oscillator based on the first retiming signal by:
• providing the input signal for injection into the previous delay stage in response to a first logic state of the oscillation waveform appearing at the selected delay stage;
• and
• providing a complementary input signal for injection into the previous delay stage in response to a second logic state of the oscillation waveform appearing at the selected delay stage.