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US 10,713,192 B2Granted
Data transmission system and data transmission method
AssigneeKinetic Technologies
InventorsMaurizio Paganini, Alan Kobayashi, Ramakrishna Chilukuri, Rahul Kumar Agarwal, Nobuhiro Yanagisawa, Sujan Valiyaka Thomas
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Abstract
A data transmission system includes a transmitter having a first switching re-timer and a receiver having a second switching re-timer. The first switching re-timer is configured to double a link rate per lane and halve the number of lanes, and the second switching re-timer is configured to halve the doubled link rate and double the halved number of lanes.
Claims25
A universal serial bus (USB) transmission device, comprising:
- a first interface configured to receive display port (DP) data via M lanes at a first link rate, wherein M is an integer greater than 1;
- and
- a switching re-timer including
- a plurality of de-serializer circuits configured to de-serialize the received DP data,
- a plurality of decoder circuits configured to decode the de-serialized DP data,
- a plurality of multiplexer circuits configured to multiplex the de-serialized DP data received via each of the M lanes into N lanes, wherein N is an integer value equal to M/2,
- a plurality of encoder circuits configured to encode the multiplexed DP data, and
- a plurality of serializer circuits configured to serialize the encoded multiplexed DP data and output the serialized multiplexed DP data on each of the N lanes at a second link rate, wherein the second link rate is equal to the first link rate multiplied by M/N.
5 more elements
A universal serial bus (USB) reception device, comprising:
- a first interface configured to receive display port (DP) data via M lanes at a first link rate, wherein M is an integer greater than 1;
- a switching re-timer including
- a plurality of de-serializer circuits configured to de-serialize the received DP data,
- a plurality of decoder circuits configured to decode the de-serialized DP data,
- a plurality of de-multiplexer circuits configured to demultiplex the de-serialized DP data received via each of the M lanes into N lanes, wherein N is an integer value equal to M multiplied by 2,
- a plurality of encoder circuits configured to encode the demultiplexed DP data, and
- a plurality of serializer circuits configured to serialize the encoded demultiplexed DP data and output the serialized demultiplexed DP data on each of the N lanes at a second link rate, wherein the second link rate is equal to the first link rate multiplied by M/N.
4 more elements
A data transmission system comprising:
- a universal serial bus (USB) transmission device, comprising:
- a first interface configured to receive display port (DP) data via M lanes at a first link rate, wherein M is an integer greater than 1;
- a first switching re-timer including
- a plurality of first de-serializer circuits configured to de-serialize the received DP data,
- a plurality of first decoder circuits configured to decode the de-serialized DP data,
- a plurality of multiplexer circuits configured to multiplex the de-serialized DP data received via each of the M lanes into N lanes, wherein N is an integer value equal to M/2,
- a plurality of first encoder circuits configured to encode the multiplexed DP data, and
- a plurality of first serializer circuits configured to serialize the encoded multiplexed DP data and output the serialized multiplexed DP data on each of the N lanes at a second link rate, wherein the second link rate is equal to the first link rate multiplied by M/N;
- and
- a USB reception device, comprising:
- a second interface configured to receive the DP data output from the USB transmission device on Y lanes at the second link rate, wherein Y is an integer greater than 1;
- a second switching re-timer including
- a plurality of second de-serializer circuits configured to de-serialize the received DP data,
- a plurality of second decoder circuits configured to decode the de-serialized DP data,
- a plurality of de-multiplexer circuits configured to demultiplex the de-serialized DP data received via each of the Y lanes into Z lanes, wherein Z is an integer value equal to Y multiplied by 2,
- a plurality of second encoder circuits configured to encode the demultiplexed DP data, and
- a plurality of second serializer circuits configured to serialize the encoded demultiplexed DP data and output the serialized demultiplexed DP data on each of the Z lanes at the first link rate.
14 more elements
Dependencies are inferred from the claim text.