US 10,712,770 B1 · Clock phase aligner for high speed data serializers

Abstract

Apparatus and associated methods relate to a high-speed data serializer with a clock calibration module including a main multiplexer (MMUX), a replicated multiplexer (RMUX), a duty cycle calibration module (DCC), and a set of adjustable delay lines (ADLs), the ADLs generating calibrated clocks from a set of system clocks, the DCC sensing duty cycle and phase of the calibrated clocks. In an illustrative example, the DCC may generate error signals indicative of deviation from an expected duty cycle using low-pass filters. The error signals control the ADLs, which may provide continuous corrections to the calibrated clocks, for example. The MMUX and RMUX may receive the calibrated clocks, the RMUX generating a duty cycle indicating clock-to-data phasing, the MMUX providing live data multiplexing, for example. Various multiplexer calibration schemes may reduce jitter, which may facilitate increased data rates associated with high-speed serial data streams.

Claims20

Dependent claims

A multiplexer-clock phase-alignment system for an integrated circuit, the system comprising:

a) a replica multiplexer (RMUX) configured to receive a replica of input data bus to generate a replica serial data output signal (RDout) in response to a multiphase RMUX control input;
b) a duty cycle calibration (DCC) processing circuit configured to receive the replica serial data output signal RDout and the multiphase RMUX control input, wherein the DCC processing circuit is further configured to generate a delay control signal in response to sensing duty cycle errors in the multiphase RMUX control input;
c) an adjustable delay line circuit (ADL) configured to update the multiphase RMUX control input received by the replica multiplexer by selectively delaying component signals of the multiphase RMUX control input in response to the delay control signal;
and,
d) a main multiplexer (MMUX) fabricated on a common substrate with the RMUX and configured to replicate the multiplexer operation of the RMUX in response to the multiphase RMUX control input.

2 more elements

A method to align multiple-phase clocks for a multiplexer on an integrated circuit, the method comprising:

a) receiving, with a replica multiplexer (RMUX), a replica of input data bus to generate a replica serial data output signal (RDout) in response to a multiphase RMUX control input;
b) receiving, with a duty cycle calibration (DCC) processing circuit, the replica serial data output signal RDout and the multiphase RMUX control input;
c) generating, with the duty cycle calibration (DCC) processing circuit, a delay control signal in response to sensing duty cycle errors in the multiphase RMUX control input;
d) updating, with an adjustable delay line circuit (ADL), the multiphase RMUX control input received by the replica multiplexer by selectively delaying component signals of the multiphase RMUX control input in response to the delay control signal;
and,
e) replicating, with a main multiplexer (MMUX) fabricated on a common substrate with the RMUX, the multiplexer operation of the RMUX in response to the multiphase RMUX control input.

3 more elements

Dependencies are inferred from the claim text.

Clock phase aligner for high speed data serializers

Life of this patent

Clock phase aligner for high speed data serializers

Life of this patent

Abstract

Claims20