Printed circuit board connection for integrated circuits using two routing layers

A printed circuit board comprising:

• an external layer that includes multiple integrated circuit ICs installed thereon;
• a first trace routing layer comprising a first conductive trace that is routed along a first path from a first IC to a second IC;
• a second trace routing layer comprising a second conductive trace that is routed along a second path from the first IC to the second IC, wherein the first conductive trace crosses over or under the second conductive trace at a point between the first IC and the second IC;
• a first via region comprising one or more first vias that extend from the first trace routing layer to the second trace routing layer, the first via region being within a first perimeter that includes (i) a first portion of the first conductive trace that extends from a first starting point at the first IC to the point at which the first conductive trace crosses over or under the second conductive trace and (ii) a first portion of the second conductive trace that extends from the point at which the first conductive trace crosses over or under the second conductive trace to a first end point at the first IC;
• and
• a second via region comprising one or more second vias that extend from the first trace routing layer to the second trace routing layer, the second via region being within a second perimeter that includes (i) a second portion of the first conductive trace that extends from a second starting point at the second IC to the point at which the first conductive trace crosses over or under the second conductive trace and (ii) a second portion of the second conductive trace that extends from the point at which the first conductive trace crosses over or under the second conductive trace to a second end point at the second IC.

A board comprising:

• a first layer that includes multiple integrated circuit (IC) installation regions that are each configured to receive an IC;
• a second layer comprising a first conductive trace that is routed along a first path from a first IC installation region to a second IC installation region;
• a third layer comprising a second conductive trace that is routed along a second path from the first IC installation region to the second IC installation region, wherein the first conductive trace crosses over or under the second conductive trace at a point between the first IC installation region and the second IC installation region;
• a first via region comprising one or more first vias that extend from the second layer to the third layer, the first via region being within a first perimeter that includes (i) a first portion of the first conductive trace that extends from a first starting point at the first IC installation region to the point at which the first conductive trace crosses over or under the second conductive trace and (ii) a first portion of the second conductive trace that extends from the point at which the first conductive trace crosses over or under the second conductive trace to a first end point at the first IC installation region;
• and
• a second via region comprising one or more second vias that extend from the second layer to the third layer, the second via region being within a second perimeter that includes (i) a second portion of the first conductive trace that extends from a second starting point at the second IC installation region to the point at which the first conductive trace crosses over or under the second conductive trace and (ii) a second portion of the second conductive trace that extends from the point at which the first conductive trace crosses over or under the second conductive trace to a second end point at the second IC installation region.