Analog-to-digital converter and solid-state image sensor
AssigneeSharp Kabushiki Kaisha
InventorsTakeo Ushinaga, Yoshinao Morikawa
Life of this patent
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Abstract
[Object] To prevent code skipping in decoding. [Solution] Included are a low-order bit latch unit (63) that latches digital code data as a low-order bit, a high-order bit counter unit (64) that counts one or both of edges of a control signal corresponding to a reference clock, and stops counting of high-order bits, triggered by output of a comparator (62) being inverted, a low-order bit decoding signal latch unit (65) that latches a low-order bit decoding signal, and a signal processing unit (8).
Claims4
An analog-to-digital converter that is disposed for at least one column or at least one of unit pixels, and converts input analog signals into digital signals, the analog-to-digital converter comprising:
- a comparator that compares voltage of the analog signals with a reference voltage of which a voltage value varies in accordance with a reference clock;
- a low-order bit latch unit that latches a digital code corresponding to the reference clock as a low-order bit, triggered by output of the comparator being inverted;
- a high-order bit counter unit that counts one or both of edges of a control signal corresponding to the reference clock, and stops counting of high-order bits, triggered by output of the comparator being inverted;
- a low-order bit decoding signal latch unit that latches a low-order bit decoding signal corresponding to the reference clock;
- and
- a signal processing unit that compares a value of the low-order bit decoding signal that has been latched and a value of a least significant bit of the high-order bits to detect code skipping, and corrects the detected code skipping.
Dependencies are inferred from the claim text.