Hardware security accelerator

An integrated circuit (IC), comprising:

• a packet type detection circuit that is configurable to determine a type of a packet based on header portions of the packet, and to generate a packet type identifier of the packet;
• a security circuit configured to perform security processing of the packet to provide a security result;
• and
• a configuration circuit arranged to extract a transaction identifier (TID) from a read response packet, to use a TID data structure to map the extracted TID to a read address to determine a cryptographic parameter based on the read address, and to configure the security circuit according to the type of the packet and according to the cryptographic parameter.

A hardware circuit-implemented method, the method comprising:

• determining protocols of headers of a packet;
• for a read packet to be transmitted to a storage system, updating a transaction identifier (TID) data structure for the read packet to include a mapping of a TID for the read packet to a read address contained in the read packet;
• extracting a TID from a return packet from the storage system and accessing the TID data structure using the extracted TID to generate controls signals based on the determined protocols of the headers and a read address mapped to the TID in the TID data structure;
• performing, by a configurable security engine, a security processing of the packet according to the determined protocols of the headers and according to cryptographic parameters from the TID data structure for the TID for the packet;
• and
• modifying, by a hardware circuit, the read address in the TID data structure to generate a next expected read address.