Digital power amplification circuit

A digital power amplification circuit comprising:

• a decoding block configured to receive a first stream of digital codes and to derive from the first stream a second stream of digital codes, the decoding block comprising a decoder configured to decode the digital codes of the first stream and the second stream at a first clock rate,
• a main digital power amplifier configured to receive the decoded digital codes of the first stream,
• an upsampler configured to upsample the decoded digital codes of the second stream to a second clock rate that is greater than the first clock rate,
• an auxiliary digital power amplifier configured to receive the decoded digital codes of the second stream upsampled to the second clock rate, and
• a summer configured to sum (i) a main output signal of the main digital power amplifier and (ii) an auxiliary output signal of the auxiliary digital power amplifier,
• wherein the first stream of digital codes comprise amplitude information of the sum of the main output signal and the auxiliary output signal.

A digital power amplification circuit comprising:

• a decoding block configured to receive a first stream of digital codes and to derive from the first stream a second stream of digital codes, the decoding block comprising a decoder configured to decode the digital codes of the first stream and the second stream at a first clock rate, wherein the decoding block is configured to derive the second stream of digital codes from the first stream by computing a difference between a first code of the first stream and a second code of the first stream that immediately precedes the first code within the first stream,
• a main digital power amplifier configured to receive the decoded digital codes of the first stream,
• an upsampler configured to upsample the decoded digital codes of the second stream to a second clock rate that is greater than the first clock rate,
• an auxiliary digital power amplifier configured to receive the decoded digital codes of the second stream upsampled to the second clock rate, and
• a summer configured to sum (i) a main output signal of the main digital power amplifier and (ii) an auxiliary output signal of the auxiliary digital power amplifier.