Techniques for synchronizing slave devices
AssigneeQUALCOMM Incorporated
InventorRadu Pitigoi-Aron
Life of this patent
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Abstract
Disclosed are methods and apparatus for calculating sensor timing corrections at a sensor device. The methods and apparatus determine a sampling period as a number of cycles of an internal clock counted while a configured number of samples is captured in a slave device, determine a time interval between samples using an offset from a time of an observed occurrence of a hardware event on a communication link, the offset being received in a command from a master device, and adjust the time interval between samples by iterative digital approximation to correct for differences between timing of the slave device and the master device while concurrently calculating a watermark time corresponding to a sample start time configured by the master device for one or more slave devices.
Claims26
A method for calculating sensor timing corrections, comprising:
- determining a synchronization period as a number of cycles of an internal clock counted while a configured number of samples is captured in a slave device;
- receiving information defining an offset from a time of an observed occurrence of a hardware synchronization event on a communication link, the offset being received in a command from a master device, wherein the information defining the offset includes a resolution ratio used to calculate resolution of steps used to adjust the synchronization period;
- and
- correcting sensor timing by adjusting the synchronization period based on the hardware synchronization event and the offset using a first iterative digital approximation while adjusting a watermark time corresponding to a sample start time using a second iterative digital approximation proportionate to the first iterative digital approximation,
- wherein the sample start time is configured by the master device for one or more slave devices.
A sensor comprising:
- a communications transceiver coupled to a serial bus;
- and
- combinational logic configured to:
- determine a synchronization period as a number of cycles of an internal clock counted while a configured number of samples is captured in the sensor;
- receive information defining an offset from a time of an observed occurrence of a hardware synchronization event on a communication link, the offset being received in a command from a master device, wherein the information defining the offset includes a resolution ratio used to calculate resolution of steps used to adjust the synchronization period;
- and
- correct sensor timing by adjusting the synchronization period based on the hardware synchronization event and the offset using a first iterative digital approximation while adjusting a watermark time corresponding to a sample start time using a second iterative digital approximation proportionate to the first iterative digital approximation,
- wherein the sample start time is configured by the master device for one or more slave devices.
A slave device, comprising:
- means for determining a synchronization period as a number of cycles of an internal clock counted while a configured number of samples is captured in the slave device;
- means for receiving information defining an offset from a time of an observed occurrence of a hardware synchronization event on a communication link, the offset being received in a command from a master device, wherein the information defining the offset includes a resolution ratio used to calculate resolution of steps used to adjust the synchronization period;
- and
- means for correcting sensor timing,
- wherein the sensor timing is corrected by adjusting the synchronization period based on the hardware synchronization event and the offset using a first iterative digital approximation while adjusting a watermark time corresponding to a sample start time using a second iterative digital approximation proportionate to the first iterative digital approximation, and
- wherein the sample start time is configured by the master device for one or more slave devices.
A non-transitory processor-readable storage medium having code stored thereon that, when executed by a processor of a slave device, causes the processor to:
- determine a synchronization period as a number of cycles of an internal clock counted while a configured number of samples is captured in the slave device;
- receive information defining an offset from a time of an observed occurrence of a hardware synchronization event on a communication link, the offset being received in a command from a master device, wherein the information defining the offset includes a resolution ratio used to calculate resolution of steps used to adjust the synchronization period;
- and
- correct sensor timing by adjusting the synchronization period based on the hardware synchronization event and the offset using a first iterative digital approximation while adjusting a watermark time corresponding to a sample start time using a second iterative digital approximation proportionate to the first iterative digital approximation,
- wherein the sample start time is configured by the master device for one or more slave devices.
Dependencies are inferred from the claim text.