A permutation circuit of a quasi-cyclic low-density parity check (QC-LDPC) decoder of an error checking and correcting circuit of a storage controller, wherein the storage controller is configured to control a storage device having a rewritable non-volatile memory module, and the QC-LDPC decoder is configured to perform a decoding procedure on a target codeword, wherein the storage controller further comprising:
- a memory interface control circuit, configured to couple to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of physical pages, and the size of each of the physical pages is identified as a page size, wherein the physical page is configured to store a plurality of codewords, and the target codeword is read from a target physical page among the physical pages, wherein a length of each of the codewords is obtained as a codeword length according to the amount of the codewords and the page size;
- and
- a processor, coupled to the error checking and correcting circuit and the memory interface control circuit, wherein the memory interface control circuit transmits the target codeword read from the rewritable non-volatile memory module to the error checking and correcting circuit, and the processor is configured to instruct the error checking and correcting circuit to perform the decoding procedure on the target codeword,
- wherein the permutation circuit comprises a plurality of selectors, a plurality of routing wires connecting to each of the selectors, a plurality of input ends, and a plurality of output ends,
- wherein a predetermined check matrix of the QC-LDPC decoder is identified, and the check matrix comprises M×N sub-matrices, wherein each of the sub-matrices is a Z×Z matrix, wherein Z is a default dimension value of each of the sub-matrices, and the default dimension value is a quotient obtained by dividing the codeword length with N, wherein a first value is calculated according to the default dimension value,
- wherein a second permutation network for disposing the selectors and routing wires into the permutation circuit is constructed by removing a target first permutation layer from a first permutation network,
- wherein the first permutation network is identified according to the first value, the default dimension value, and a shift type of the check matrix, wherein the first permutation network comprises a plurality of first permutation layers arranged sequentially, and each of the first permutation layers has the same amount of first nodes, wherein the amount of the first permutation layers is set by the first value, and the amount of the first nodes of each of the first permutation layers is set by the default dimension value, wherein every first node of one of the first permutation layers connects to a pair of first nodes of the next one first permutation layer among the first permutation layers,
- wherein the target first permutation layer among the first permutation layers of the first permutation network according to the shift type of the check matrix,
- wherein a plurality of selectors are disposed on a plurality of second nodes of the second permutation network of the permutation circuit, and a plurality of routing wires are disposed into the permutation circuit to connect the selectors according to the second permutation network, wherein the selectors further respectively connect to a decoding controller of the QC-LDPC decoder, wherein the decoding controller is configured to control the selectors to shift a plurality of first variable groups corresponding to the target codeword as a plurality of second variable groups, wherein the second variable groups are respectively shifted according to a plurality of target offsets corresponding to the first variable groups and the second variable groups, wherein the target offsets are identified according to the check matrix.