Second-order delta-sigma modulator and transmission apparatus

A transmission apparatus comprising

• a second-order delta-sigma modulator including:
• a first accumulator that receives an input bit signal;
• a second accumulator that receives a sum bit output of the first accumulator;
• a parallel higher-bit processing part that receives, as first and second carry inputs, first and second carry outputs outputted from the first and the second accumulators, and outputs a quantized output, wherein
• the parallel higher-bit processing part comprises:
• first to M-th (M is an integer not less than 2) addition and determination processing sections, each of which receives the first and the second carry inputs and first and second state inputs, and outputs a quantized output and first and second state outputs;
• a first selector that receives M sets of the first and the second state outputs outputted from the first to the M-th addition and determination processing sections, selects a set from the M sets of the first and the second state outputs based on a control signal, and outputs the set selected;
• and
• a second selector that receives M quantized outputs outputted from the first to the M-th addition and determination processing sections, selects one quantized output from the M quantized outputs based on the control signal and outputs the quantized output selected,
• the output of the first selector being used as the control signal in the first and the second selectors.

A second-order delta-sigma modulation method, comprising:

• a parallel higher-bit processing step of receiving first and second carry outputs from a first accumulator that receives an input bit signal and a second accumulator that receives a sum bit output of the first accumulator as first and second carry inputs, and outputting a quantized output, wherein
• the parallel higher-bit processing step includes:
• first to M-th (M is an integer not less than 2) addition/determination processing steps, each receiving the first and the second carry inputs and first and second state inputs, and outputting a quantized output and first and second state outputs;
• receiving M sets of the first and the second state outputs outputted in the first to the M-th addition/determination processing steps, selecting one set based on a control signal, and outputting the selected set;
• receiving M quantized outputs outputted in the first to the M-th addition/determination processing steps, selecting one quantized output according to the delayed control signal, and outputting the selected quantized output;
• and
• delaying the first and the second state outputs selected by the first selector and using the delayed signals as the control signal for the first and the second selectors.