Interleaving method for analog to digital converters

An interleaved successive approximation register (SAR) analog-to-digital converter (ADC) circuit, the SAR ADC circuit comprising:

• multiple sub-ADC circuits, each sub-ADC circuit including:
• a digital-to-analog (DAC) circuit that includes weighted circuit components;
• and
• a switch circuit configured to sample an analog input signal for conversion;
• a comparator circuit configured to compare a voltage of one or more of the weighted components of the DAC circuits of the multiple sub-ADC circuits to the sampled analog input signal as part of a bit trial of an analog-to-digital (A/D) conversion of the sub-ADC circuits;
• control logic circuitry configured to advance the multiple sub-ADC circuits through time-interleaved acquisition phases, conversion phases, and tracking phases;
• wherein an acquisition phase of a first sub-ADC circuit samples the analog input signal, a conversion phase of the first sub-ADC circuit converts the sampled analog signal to a digital value using bit trials, and the control logic circuitry is configured to update the first sub-ADC circuit with most recent A/D conversion information by a different sub-ADC circuit during a tracking phase of the first sub-ADC circuit before the acquisition phase of the first sub-ADC circuit.