US 10,707,872 B1 · Digital buffer circuit

Abstract

Circuits and techniques for buffering a digital signal are disclosed. The circuits and techniques allow a digital buffer circuit to accommodate a range of output voltages while maintaining a delay between input and output that is suitable for digital communications. The disclosed circuits and techniques utilize a combination of low voltage switches and high voltage switches. The low voltage switches dominate the buffering process when the buffer drives external circuitry (e.g., a communications bus) having a low voltage then, and the high voltage switches dominate the buffering process when the buffer drives external circuitry having a high voltage. The high voltage and low voltage switches configure themselves automatically based on an operating condition determined by the voltage level of the output with respect to the voltage level of the input.

Claims20

Dependent claims

A buffer circuit, the buffer circuit comprising:

a plurality of stages each coupled to a high voltage (HV) supply and a low voltage (LV) supply, wherein each stage includes:
a push-pull circuit that includes a HV PMOS transistor controllable to pull-up an output of the stage to the HV supply when the buffer circuit is in a HV operating condition;
and
an LV pull-up circuit that includes an LV PMOS transistor controllable to pull-up the output of the stage to the LV supply when the buffer circuit is in an LV operating condition, wherein in the HV operating condition, the LV supply is decoupled from the HV supply by a LV NMOS transistor that has a HV source terminal coupled to the output of the stage.

1 more element

Dependencies are inferred from the claim text.

Digital buffer circuit

Life of this patent

Digital buffer circuit

Life of this patent

Abstract

Claims20