MOS power transistors in parallel channel configuration

A circuit, comprising:

• a first MOS power transistor comprising a first gate terminal, a first drain terminal, and a first source terminal,
• a second MOS power transistor comprising a second gate terminal, a second drain terminal, and a second source terminal, and
• a switch connected in-between the first gate terminal and the second gate terminal and configured to selectively couple the first gate terminal and the second gate terminal,
• wherein the switch comprises a first further MOS transistor and a second further MOS transistor,
• wherein a body terminal of the first further MOS transistor is coupled with the first source terminal,
• wherein a body terminal of the second further MOS transistor is coupled with the second source terminal,
• wherein an source terminal of the first further MOS transistor is coupled with the first gate terminal,
• wherein a source terminal of the second further MOS transistor is coupled with the second gate terminal, and
• wherein a drain terminal of the first further MOS transistor is coupled with a drain terminal of the second further MOS transistor.

A circuit, comprising:

• a first MOS power transistor comprising a first gate terminal, a first drain terminal, and a first source terminal,
• a second MOS power transistor comprising a second gate terminal, a second drain terminal, and a second source terminal, and
• a switch connected in-between the first gate terminal and the second gate terminal and configured to selectively couple the first gate terminal and the second gate terminal,
• wherein the first MOS power transistor and the second MOS power transistor are n-type,
• wherein the switch comprises MOS transistors which are p-type,
• wherein the at least one MOS transistor has a threshold voltage, and
• wherein the threshold voltage of the at least one further MOS transistor is smaller than the threshold voltages of the first MOS power transistor and the second MOS power transistor.

A circuit, comprising:

• a first MOS power transistor having a first gate terminal, a first drain terminal, and a first source terminal,
• a second MOS power transistor having a second gate terminal, a second drain terminal, and a second source terminal, and
• a control circuitry configured to detect a failure condition of at least one of the first MOS power transistor and the second MOS power transistor,
• wherein the control circuitry is configured to provide a first control signal to the first gate terminal to operate the first MOS power transistor in a high-resistivity state and to provide a second control signal to the second gate terminal to operate the second MOS power transistor in a high-resistivity state, in response to said detecting of the failure condition.

A method of operating a circuit that includes at least two MOS power transistors, wherein the circuit includes:

• a first MOS power transistor comprising a first gate terminal, a first drain terminal, and a first source terminal, a second MOS power transistor comprising a second gate terminal, a second drain terminal, and a second source terminal, a switch connected in-between the first gate terminal and the second gate terminal and configured to selectively couple the first gate terminal and the second gate terminal, a first clamp between the first drain terminal and the first gate terminal, the first clamp defining a first clamp voltage, and a second clamp between second drain terminal and the
• second gate terminal, the second
• clamp defining a second clamp voltage, wherein the second clamp voltage does not match the first clamp voltage, the method comprising:
• detecting a failure condition of at least one of the at least two MOS power transistors, and in response to said detecting of the failure condition:
• synchronizing the first and second gate terminals of the at least two MOS power transistors.