Double data rate circuit and data generation method implementing precise duty cycle control

A data generation method adopted by a double data rate circuit comprising a clock generator, a clock divider and a multiplexer, the data generation method comprising:

• the clock generator receiving a source clock signal to generate a pair of complementary clock signals;
• the clock divider generating four multiphase clock signals using only single-edge transitions of the pair of complementary clock signals, the four multiphase clock signals being out-of-phase by 90° with each other;
• and
• the multiplexer multiplexing multiple data bits into an output data stream by sequentially selecting and deselecting each data bit of the multiple data bits upon a first edge transition and a second edge transition of two of the four multiphase clock signals, respectively, and outputting each selected data bit as the output data stream;
• wherein the multiplexer comprises four 3-input NAND gates and one 4-input NAND gate coupled thereto;
• inputs of the 3-input NAND gates are matched in pull-up paths and pull-down paths, and inputs of the 4-input NAND gate are matched in pull-up paths and pull-down paths;
• and
• the method further comprises:
• each of the four 3-input NAND gates receiving one of four multiple data bits and two of the four multiphase clock signals, starting outputting the received data bit upon the first edge transition of one of the two received multiphase clock signals, and stopping from outputting the received data bit upon the second edge transition of another one of the two received multiphase clock signals, the two received multiphase clock signals being out-of-phase by 90°;
• and
• the 4-input NAND gate receiving respective output signals from the four 3-input NAND gates to generate the output data stream.

A double data rate circuit comprising:

• a clock generator, configured to receive a source clock signal to generate a pair of complementary clock signals;
• a clock divider, coupled to the clock generator, and configured to generate four multiphase clock signals using only single-edge transitions of the pair of complementary clock signals, the four multiphase clock signals being successively out-of-phase by 90°;
• and
• a multiplexer, coupled to the clock divider, and configured to multiplex multiple data bits into an output data stream by sequentially selecting and deselecting each data bit of the multiple data bits upon a first edge transition and a second edge transition of two of the four multiphase clock signals, respectively, and outputting each selected data bit as the output data stream;
• wherein the multiplexer comprises four 3-input NAND gates and one 4-input NAND gate coupled thereto;
• each of the four 3-input NAND gates is configured to receive one of four multiple data bits and two of the four multiphase clock signals, start outputting the received data bit upon the first edge transition of one of the two received multiphase clock signals, and stop outputting the received data bit upon the second edge transition of another one of the two received multiphase clock signals, the two received multiphase clock signals being out-of-phase by 90°;
• the 4-input NAND gate is configured to receive respective output signals from the four 3-input NAND gates to generate the output data stream;
• inputs of the 3-input NAND gates are matched in pull-up paths and pull-down paths, and inputs of the 4-input NAND gate are matched in pull-up paths and pull-down paths;
• and
• each of the four 3-input NAND gates comprises:
• a first P-type transistor having a control terminal configured to receive a first input signal, a first terminal coupled to a power supply terminal, and a second terminal configured to output an output signal;
• a second P-type transistor having a control terminal configured to receive a second input signal, a first terminal coupled to the power supply terminal, and a second terminal configured to output the output signal;
• a third P-type transistor having a control terminal configured to receive a third input signal, a first terminal coupled to the power supply terminal, and a second terminal configured to output the output signal;
• a first N-type transistor having a control terminal configured to receive the first input signal, a first terminal coupled to the second terminal of the first P-type transistor, and a second terminal;
• a second N-type transistor having a control terminal configured to receive the second input signal, a first terminal coupled to the second terminal of the first N-type transistor, and a second terminal;
• a third N-type transistor having a control terminal configured to receive the third input signal, a first terminal coupled to the second terminal of the second N-type transistor, and a second terminal coupled to a ground terminal;
• a fourth N-type transistor having a control terminal configured to receive the second input signal, a first terminal coupled to the second terminal of the second P-type transistor, and a second terminal;
• a fifth N-type transistor having a control terminal configured to receive the third input signal, a first terminal coupled to the second terminal of the fourth N-type transistor, and a second terminal;
• a sixth N-type transistor having a control terminal configured to receive the first input signal, a first terminal coupled to the second terminal of the fifth N-type transistor, and a second terminal coupled to the ground terminal;
• a seventh N-type transistor having a control terminal configured to receive the third input signal, a first terminal coupled to the second terminal of the third P-type transistor, and a second terminal;
• an eighth N-type transistor having a control terminal configured to receive the first input signal, a first terminal coupled to the second terminal of the seventh N-type transistor, and a second terminal;
• and
• a ninth N-type transistor having a control terminal configured to receive the second input signal, a first terminal coupled to the second terminal of the eighth N-type transistor, and a second terminal coupled to the ground terminal.