Synchronous mirror delay circuit and synchronous mirror delay operation method
AssigneeWinbond Electronics Corp.
InventorWen-Chiao Ho
Life of this patent
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Abstract
A synchronous mirror delay (SMD) circuit is provided in the invention. The SMD circuit includes a delay monitor circuit (DMC), a forward delay circuit, a first shift circuit, a backward delay circuit, a second shift circuit and a clock-frequency-checker (CSC) circuit. The CSC circuit is coupled to the first shift circuit and the second shift circuit. The CSC circuit determines whether the frequency of the external input clock signal is slower than the frequency of the reference clock signal to generate a judgment result, and the CSC circuit transmits the judgment result to the first shift circuit and the second shift circuit. The first shift circuit and the second shift circuit determine whether to delay the external input clock signal according to the judgment result.
Claims14
A synchronous mirror delay (SMD) circuit, comprising:
- a delay monitor circuit (DMC), coupled to an input buffer;
- a forward delay circuit;
- a first shift circuit;
- coupled to the DMC and the forward delay circuit;
- a backward delay circuit;
- a second shift circuit, coupled to the backward delay circuit and a clock driver;
- and
- a clock-frequency-checker (CSC) circuit, coupled to the first shift circuit and the second shift circuit,
- wherein the CSC circuit determines whether the frequency of an external input clock signal is slower than the frequency of a reference clock signal to generate a judgment result, and the CSC circuit transmits the judgment result to the first shift circuit and the second shift circuit, and
- wherein the first shift circuit and the second shift circuit determine whether to delay the external input clock signal based on the judgment result.
A synchronous mirror delay (SMD) operation method, applied to an SMD circuit, and comprising:
- determining, by a clock-frequency-checker (CSC) circuit of the SMD circuit, whether the frequency of an external input clock signal is slower than the frequency of a reference clock signal to generate a judgment result;
- transmitting the judgment result to a first shift circuit and a second shift circuit of the SMD circuit;
- and
- determining, by the first shift circuit and the second shift circuit, whether to delay the external input clock signal according to the judgment result.
Dependencies are inferred from the claim text.