Ultra-low voltage level shifter

A structure comprising a voltage level shifter circuit which includes a first current mirror leg circuit and a second current mirror leg circuit, wherein:

• the first current mirror leg circuit receives an input signal on a low voltage power supply and level shifts the input signal to a high voltage power supply which is at a greater voltage than the low voltage power supply;
• the high voltage power supply is output from the second current mirror leg circuit;
• the first current mirror leg circuit comprises a first NOR gate and a first transistor;
• the first NOR gate receives an inverted enable signal and an input signal and outputs a NETA signal;
• and
• the first current mirror leg comprises a second transistor which is a dual gate, thick oxide, high voltage transistor and has a drain connected to a drain of the first transistor.

A method, comprising:

• receiving an input signal, a bias signal, a bias voltage generator output signal, an inverted input signal, and an inverted enable signal at a voltage level shifter circuit, wherein the voltage level shifter circuit includes a first current mirror leg circuit and a second current mirror leg circuit;
• and
• level shifting the input signal to a higher voltage than the input signal by using a differential current between the first current mirror leg circuit and the second current mirror leg circuit,
• wherein
• the higher voltage is a multiple voltage value of the input signal, and
• at least one of the first current mirror leg circuit or the second current mirror leg circuit includes a dual gate transistor.

A structure comprising a voltage level shifter circuit which includes a first current mirror leg circuit and a second current mirror leg circuit, wherein:

• the first current mirror leg circuit receives an input signal on a low voltage power supply and level shifts the input signal to a high voltage power supply, which is at a greater voltage than the low voltage power supply;
• the high voltage power supply is output from the second current mirror leg circuit;
• the first current mirror leg circuit comprises a first transistor and a first NOR gate;
• the second current mirror leg circuit comprises a second transistor and a second NOR gate;
• the first transistor and the second transistor are gated with a bias signal;
• the first NOR gate is connected to a source of the first transistor and receives the input signal;
• the second NOR gate is connected to a source of the second transistor and receives an inverted version of the input signal;
• an output of the first transistor is based on the bias signal and an output of the first NOR gate;
• and
• an output of the second transistor is based on the bias signal and an output of the second NOR gate.