Ring voltage-controlled oscillator and phase-locked loop

A ring voltage control oscillator, comprising:

• a conversion unit configured to receive an externally controlled voltage signal, and output a control current signal;
• cascaded multistage delay units configured to receive the control current signal outputted by the conversion unit;
• wherein the delay unit comprises two signal input terminals and two signal output terminals;
• a first signal output terminal and a second signal output terminal of the delay unit are correspondingly connected to a first signal input terminal and a second signal input terminal of a next stage of the delay unit, respectively;
• a first signal output terminal and a second signal output terminal of a last stage of the delay unit are correspondingly connected to a second signal input terminal and a first signal input terminal of a first stage of the delay unit, respectively;
• multistage isolation buffer units configured to receive the control current signal outputted by the conversion unit;
• wherein the isolation buffer unit comprises two signal input terminals and two signal output terminals;
• a first signal input terminal and a second signal input terminal of the isolation buffer unit are connected to a first signal output terminal and a second signal output terminal of the same stage of the delay unit, respectively;
• wherein clock signals outputted by first signal output terminals of two adjacent stages of the isolation buffer units have a first phase difference;
• wherein second signal output terminals of two adjacent stages of the isolation buffer units correspondingly output clock signals having a second phase difference equal to the first phase difference;
• wherein the delay unit comprises a first inverting circuit, a second inverting circuit, a first MOS transistor, a second MOS transistor, and a trans-coupling circuit;
• an input terminal and an output terminal of the first inverting circuit correspondingly serve as the first signal input terminal and the second signal output terminal of the delay unit, respectively;
• an input terminal and an output terminal of the second inverting circuit correspondingly serve as the second signal input terminal and the first signal output terminal of the delay unit, respectively;
• both a gate and a drain of the first MOS transistor are connected to the output terminal of the first inverting circuit;
• a first control terminal of the trans-coupling circuit is connected to the output terminal of the second inverting circuit;
• a second control terminal of the trans-coupling circuit is connected to the output terminal of the first inverting circuit;
• both a gate and a drain of the second MOS transistor are connected to the output terminal of the second inverting circuit;
• both a source of the first MOS transistor and a source of the second MOS transistor are grounded, wherein the first MOS transistor and the second MOS transistor are both first conductivity type MOS transistors;
• and
• both a power supply terminal of the first inverting circuit and a power supply terminal of the second inverting circuit are connected to the power source.