Relaxation oscillator

A relaxation oscillator, comprising:

• a first comparator, comprising a first input end, a second input end, and an output end, wherein the first input end of the first comparator is coupled with a first output end of a capacitor control module, the second input end of the first comparator is coupled with an external reference threshold voltage, and the output end of the first comparator is coupled with a first input end of an SR latch;
• a second comparator, comprising a first input end, a second input end, and an output end, wherein the first input end of the second comparator is coupled with a second output end of the capacitor control module, the second input end of the second comparator is coupled with the external reference threshold voltage, and the output end of the second comparator is coupled with a second input end of the SR latch;
• the SR latch, comprising the first input end, the second input end, a first output end, and a second output end, wherein the first output end of the SR latch is coupled with a first input end of the capacitor control module, and the second output end of the SR latch is coupled with a second input end of the capacitor control module;
• and
• the capacitor control module, comprising the first input end, the second input end, a bias current input end, the first output end, the second output end, a first capacitor, and a second capacitor, wherein the bias current input end of the capacitor control module is coupled with an external bias current source;
• wherein according to the external reference threshold voltage, a first comparison signal generated by the first comparator and a second comparison signal generated by the second comparator are inputted into the SR latch to generate a control signal, and according to a bias current of the external bias current source and the control signal outputted by the SR latch, periodic charging and discharging of the first capacitor and the second capacitor are controlled to generate an oscillating signal, wherein both the first comparator and the second comparator comprising:
• a first current mirror unit, coupled with the external bias current source and configured to mirror the bias current of a bias current source;
• a second current mirror unit, coupled with the first current mirror unit and configured to mirror the bias current again after the bias current is mirrored by the first current mirror unit
• a comparator signal channel coupled with the second current mirror unit, the first input end of the comparator, and the second input end of the comparator, and the comparator signal channel configured to receive the bias current after the bias current is mirrored by the second current mirror unit, a feedback signal of the capacitor control unit, and the external reference threshold voltage and generate a comparison signal according to the bias current which has already been mirrored by the second current mirror unit, the feedback signal of the capacitor control unit, and the external reference threshold voltage;
• a third current mirror unit, coupled with the comparator signal channel and configured to convert the comparison signal outputted by the comparator signal channel into a signal capable of being inputted into a reverse unit at a single-end;
• and
• the reverse unit, coupled with the third current mirror unit and configured to amplify the comparison signal after the comparison signal is converted by the third current mirror unit and output the amplified comparison signal to the SR latch.