Input and output circuits and integrated circuits using the same

An input/output (I/O) circuit comprising:

• an input control circuit configured to apply a stress to a plurality transistors for a transmission path based on an input signal while in a test mode and configured to buffer the input signal using a drivability which is changed by the stress applied to the plurality of transistors for the transmission path to generate first and second transmission signals while in a normal mode after the test mode;
• a first signal synthesis circuit configured to drive a first node using a drivability changed by the stress to generate an inversely delayed input signal having a second logic level while in a test mode if the input signal has a first logic level, configured to output the input signal as a delayed input signal through a second node while in the normal mode, and configured to connect the first node to the second node while in the normal mode;
• a signal transmission circuit configured to buffer the delayed input signal using the drivability changed by the stress applied while in the test mode to generate the first transmission signal and configured to buffer the inversely delayed input signal using the drivability changed by the stress applied while in the test mode to generate the second transmission signal;
• and
• an output control circuit configured to drive and output an output signal according to the first and second transmission signals based on a test mode signal.