Power converter with on-resistance compensation
AssigneeApple Inc.
InventorsMichael Couleur, Andrea Acquas, Nicola Rasera
Life of this patent
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Abstract
A power converter circuit included in a computer system may charge and discharge a switch node coupled to a regulated power supply node via an inductor. During a charge cycle, the power converter circuit may generate a reference ramp signal that has an initial voltage level greater than that of the switch node. The power converter may also generate a sense ramp signal using the voltage level of the switch node, and halt the charge cycle using results of a comparison of the respective voltage levels of the reference ramp signal and the sense ramp signal.
Claims13
An apparatus, comprising:
- a voltage regulator circuit including a switch node coupled to a regulated power supply node via an inductor, wherein the voltage regulator circuit is configured to source current to the switch node during a charge cycle;
- a control circuit configured to:
- initiate the charge cycle of the switch node in response to a determination that a voltage level of the switch node is less than a reference voltage level;
- in response to initiating the charge cycle:
- amplify a filtered version of the voltage level of the switch node to generate an initial ramp voltage level that is greater than the voltage level of the switch node;
- generate a reference ramp signal using the initial ramp voltage level;
- and generate a sense ramp signal using a voltage level of an input power supply node and a result of a comparison of the voltage level of the switch node and the reference voltage level;
- and halt the charge cycle using results of a comparison of respective voltage levels of the reference ramp signal and the sense ramp signal.
A method, comprising:
- comparing a reference voltage level to a voltage level of a switch node coupled to a regulated power supply node via an inductor;
- in response to determining that the voltage level of the switch node is less than the reference voltage level:
- charging the switch node using a voltage level of an input supply node;
- generating an initial ramp voltage level by amplifying a filtered version of the voltage level of the switch node, wherein the initial ramp voltage level is greater than the voltage level of the switch node;
- generating a reference ramp signal using the initial ramp voltage level;
- and generating a sense ramp signal using a voltage level of an input power supply node and a result of comparing the voltage level of the switch node and the reference voltage level;
- and halting charging of the switch node using results of comparing respective voltage levels of the reference ramp signal and the sense ramp signal.
An apparatus, comprising:
- a voltage regulator circuit including a switch node coupled to a regulated power supply node via an inductor, wherein the voltage regulator circuit is configured to source current to the switch node during a charge cycle;
- a buffer circuit configured to buffer a voltage level of the switch node to generate a buffered signal;
- a filter circuit configured to filter the buffered signal to generate a filtered signal;
- a voltage generator circuit configured to generate, using the filtered signal, an initial ramp voltage level whose voltage is greater than a voltage level of the switch node;
- a first amplifier circuit configured to generate a bias signal using the initial ramp voltage level;
- a device configured to generate a ramp current using the bias signal;
- and a ramp generator and comparator circuit configured to:
- in response to an initiation of the charge cycle:
- generate a reference ramp signal using the initial ramp voltage level;
- generate a sense ramp signal using a voltage level of an input power supply node and a result of a comparison of the voltage level of the switch node and a reference voltage level;
- and halt the charge cycle using results of a comparison of respective voltage levels of the reference ramp signal and the sense ramp signal.
Dependencies are inferred from the claim text.