Power regulation with charge pumps

A printed circuit board assembly (PCBA) comprising:

• a switching regulator that includes:
• a first switch coupled between a power rail of the PCBA and a first terminal of an inductor of the switching regulator;
• a second switch coupled between a lower potential of the PCBA and the first terminal of the inductor of the switching regulator;
• and
• a capacitor connected between a second terminal of the inductor and the lower potential of the PCBA;
• and
• an integrated circuit that includes:
• an internal power rail coupled, via a power input node, to the second terminal of the inductor of the switching regulator;
• multiple processor cores that include a first processor core and a second processor core;
• and
• multiple charge pumps that include:
• a first charge pump coupled between the internal power rail of the integrated circuit and a first input power rail of the first processor core;
• and
• a second charge pump coupled between the internal power rail of the integrated circuit and a second input power rail of the second processor core, the second input power rail of the second processor core not coupled to the first input power rail of the first processor core,
• wherein a first frequency or first duty cycle at which the first charge pump is configured to operate is different from a second frequency or second duty cycle at which the second charge pump is configured to operate.

An integrated circuit comprising:

• a power input connected to an internal power rail of the integrated circuit;
• multiple digital loads that each have a respective input power rail that is isolated from the input power rails of others of the multiple digital loads;
• and
• multiple charge pumps that are each coupled between the internal power rail of the integrated circuit and a respective one of the input power rails, each of the multiple charge pumps comprising:
• a first pair of switches coupled in series between the internal power rail of the integrated circuit and the respective input power rail;
• a second pair of switches coupled in series between the respective input power rail and a lower potential;
• a first capacitor coupled from a common node of the first pair of switches to a common node of the second pair of switches;
• and
• a second capacitor coupled between the respective input power rail and the lower potential.

An integrated circuit comprising:

• a power input connected to an internal power rail of the integrated circuit;
• multiple processor cores that include a first processor core and a second processor core;
• multiple charge pumps that include:
• a first charge pump coupled between the internal power rail of the integrated circuit and a first input power rail of the first processor core;
• a second charge pump coupled between the internal power rail of the integrated circuit and a second input power rail of the second processor core;
• means for monitoring a voltage of the first input power rail of the first processor core;
• and
• means for altering, based on the voltage, operation of the first charge pump or the second charge pump to adjust the voltage of the first input power rail or the second input power rail;
• and
• means for monitoring an operative state of the first processor core or the second processor core;
• and
• means for suspending, based on the operative state, operation of the first charge pump or the second charge pump to idle the first processor core or the second processor core.