Light emitting display device

A light emitting display device including a plurality of sub pixel areas, wherein the plurality of sub pixel areas each having an emission area and an anode contact area adjacent to each other, comprising:

• a plurality of driving thin film transistors, wherein each of the plurality of driving thin film transistors respectively disposed in the plurality of sub pixel areas;
• a substrate supporting the plurality of driving thin film transistors;
• a plurality of connection electrode patterns overlapping the anode contact area in each sub pixel area and respectively connected with source electrodes of the driving thin film transistors as one-to-one correspondence;
• a cathode electrode overlapping the emission area in each sub pixel area and including a plurality of cathode electrode lines disposed at the emission area and a plurality of cathode electrode connection lines disposed between each of the plurality of connection electrode patterns and electrically connecting two cathode electrode lines of the plurality of cathode electrode lines adjacent to each other;
• an emission layer disposed on the cathode electrode;
• a plurality of anode electrodes disposed on the emission layer in each sub pixel area and connected with the plurality of connection electrode patterns at the anode contact area as one-to-one correspondence;
• and
• at least one cathode power line disposed on the substrate, wherein the at least one cathode power line is electrically connected with at least one of the plurality of cathode electrode lines.

A light emitting display device comprising:

• a substrate including a plurality of sub pixel areas;
• a driving thin film transistor disposed in each of the plurality of sub pixel areas wherein the driving thin film transistor having a source electrode;
• a planarization layer disposed on the substrate and configured to cover the driving thin film transistor;
• a cathode electrode and a plurality of connection electrode patterns disposed on the planarization layer, wherein the plurality of connection electrode patterns being respectively connected with source electrode of the driving thin film transistor disposed in the plurality of sub pixel areas by one-to-one correspondence;
• an emission layer disposed on the cathode electrode;
• and
• a plurality of anode electrodes disposed on the emission layer,
• wherein the plurality of connection electrode patterns are electrically separated from the cathode electrode via a bank layer.