Single-sided liner PCM cell for 3D crossbar PCM memory

A method of forming a memory array comprising:

• forming on a plurality of trench structures within a first dielectric layer, each trench of said plurality having a first conductive material layer on a bottom surface and an access device material layer formed on said first conductive material layer, a first layer of resistance-drift stabilizing liner material formed on inner sidewall surfaces in said trench, and a second sacrificial liner material formed on sidewalls adjacent to said first layer of turning liner material, each trench separated by adjacent first dielectric material structures;
• patterning and etching an opening within each trench of said plurality, said etching selective to an underlying dielectric material below said first dielectric layer;
• and each opening defining a pattern comprising a plurality of structures, each structure defining a first conductive line structure, an access device layer above the first conductive material line structure and a liner structure disposed vertically above said access layer comprising adjacent layers of said resistance-drift stabilizing liner material and sacrificial liner material, the first conductive material line layer, the access layer, and vertically disposed liner structure in sidewall alignment;
• depositing in the openings within each trench a dielectric material and planarizing a surface to render surfaces of the vertically disposed liner structure and the deposited dielectric material coplanar;
• patterning a mask structure to form a pattern of sacrificial line structures on the planarized surface, the patterned sacrificial line structures oriented in a direction perpendicular to the plurality of first conductive line structures;
• performing perpendicular cut etching to remove all dielectric material between the structures selective to the underlying first conductive material line structure;
• depositing a dielectric fill material in openings removed by said perpendicular cut etching and planarizing a surface to render top surfaces of the dielectric fill material and the mask line structures coplanar;
• performing CMP to expose a top surface of the vertically disposed adjacent layers of said resistance-drift stabilizing liner material and sacrificial liner material of each liner structure;
• removing the adjacent sacrificial liner material from each vertically disposed liner structure in the pattern to provide an opening in the vertically disposed liner structure, said opening exposing a top surface of said access device layer;
• and
• depositing a PCM material into the openings in each vertically disposed liner structure adjacent the resistance-drift stabilizing liner material to form a memory element having the resistance-drift stabilizing liner material disposed only on a single side of the PCM material, and planarizing a surface to render coplanar surfaces of the PCM material and the dielectric material;
• patterning and forming a plurality of second conductive line structures on said surface in an orientation perpendicular relative to the first conductive material line structures, said second conductive line structures contacting exposed surfaces of said memory element of adjacent elements along the first conductive line structures, said patterning and forming of said second conductive line structures rendering a 2-Dimensional cross point memory array.