Etendue enhancement for light emitting diode subpixels

A method of forming a semiconductor structure, comprising:

• forming a growth mask layer including openings therethrough on a top surface of a doped compound semiconductor layer located over a substrate;
• forming a plurality of selectively grown epitaxial semiconductor structures extending through a respective opening through the growth mask layer and having a doping of a first conductivity type;
• forming a plurality of semiconductor layer stacks on a respective selectively grown epitaxial semiconductor structure;
• forming at least one second conductivity type semiconductor material layer having a doping of a second conductivity type and on the plurality of semiconductor layer stacks;
• patterning the growth mask layer and the doped compound semiconductor layer, wherein discrete mesa base semiconductor portions including a respective patterned portion of the doped compound semiconductor are formed;
• forming a dielectric liner layer over remaining portions of the at least one second conductivity type semiconductor material layer after patterning the doped compound semiconductor layer, wherein the dielectric liner contacts sidewalls of, and laterally surrounds, the growth mask layer, and contacts sidewalls of, and laterally surrounds, the mesa base semiconductor portion, and contacts the physically exposed portion of the top surface of the substrate;
• forming a reflector layer over the dielectric liner layer, wherein the reflector layer includes sidewall portions that laterally surround a respective remaining portion of the second conductivity type semiconductor material layer and laterally surrounds the discrete mesa base semiconductor portions;
• and
• detaching a combination of one of the discrete mesa base semiconductor portions and material portions that overlie the one of the discrete mesa base semiconductor portions from the substrate as a light emitting device, wherein the one of the discrete mesa base semiconductor portions comprises a top semiconductor surface that contacts a portion of the dielectric liner and a bottom semiconductor surface on an opposite side of the top semiconductor surface.