Multiple state electrostatically formed nanowire transistors

A method, comprising:

• utilizing a planar semiconducting substrate, wherein the planar semiconducting substrate has a first face and a second face opposite the first face;
• forming a source on the first face of the substrate;
• forming a first drain on the second face of the substrate;
• forming a second drain on the second face of the substrate in a location physically separated from the first drain;
• forming four spatially separated gates on the second face of the substrate, and configuring the four gates to selectably apply an electrical potential to the substrate in either a first spatial pattern, which causes a first conductive path to be established electrostatically within the substrate from the source to the first drain, or a second spatial pattern, which causes a second conductive path to be established electrostatically within the substrate from the source to the second drain,
• wherein the first drain and the second drain are comprised in a rectangular m×n array of physically separated drains formed on the second face, where at least one of m and n is a positive integer greater than 1, and
• wherein the four gates are disposed about the rectangular array;
• and
• providing two state to gates components each configured to receive a ternary input state and in response to supply respective voltage outputs to opposing two of the four gates,
• wherein the rectangular m×n array comprises a 3×3 array, configured to act as two ternary input state, nine output state multiplexer.