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US 10,707,354 B2Granted
Semiconductor integrated circuit device
AssigneeSocionext Inc.
InventorHiroyuki Shimbo
Life of this patent
Estimating the term…
Abstract
In a standard cell including nanowire FETs, pads connected to nanowires are arranged at a predetermined pitch in X direction along which the nanowires extend. A cell width of the standard cell is an integral multiplication of the pitch. In a case where the standard cell is arranged to constitute the layout of a semiconductor integrated circuit device, the pads are regularly arranged in the X direction.
Claims15
A semiconductor integrated circuit device comprising
- at least one standard cell including at least one nanowire field effect transistor (FET),
- the nanowire FET including:
- a nanowire extending along a first direction, the nanowire being a single nanowire or including a plurality of parallelly arranged nanowires;
- pads arranged at both ends of the nanowire in the first direction, having a lower surface below a lower surface of the nanowire, and connected to the nanowire;
- and
- a gate electrode extending along a second direction perpendicular to the first direction, and surrounding a periphery of the nanowire within a predetermined range of the nanowire in the first direction, wherein:
- in the standard cell, the pads are arranged at a first pitch in the first direction, and a cell width of the standard cell that is a dimension of the standard cell in the first direction is an integral multiplication of the first pitch, and
- the nanowire FET includes p-type and n-type nanowire FETs, and the gate electrode in the p-type nanowire FET and the gate electrode in the n-type nanowire BET are integrally formed with each other, and extends linearly along the second direction.
5 more elements
A semiconductor integrated circuit device comprising
- first and second transistors that are nanowire FETs and have the same conductivity type,
- each of the first and second transistors including:
- a nanowire extending along a first direction, the nanowire being a single nanowire or including a plurality of parallelly arranged nanowires;
- first and second pads arranged at both ends of the nanowire in the first direction at a first pitch, having a lower surface below a lower surface of the nanowire, and connected to the nanowire;
- a gate electrode extending along a second direction perpendicular to the first direction, and surrounding a periphery of the nanowire within a predetermined range of the nanowire in the first direction, wherein
- the first and second transistors are connected together in series, share the second pads, and arranged adjacent to one another in the first direction.
3 more elements
A semiconductor integrated circuit device comprising
- first and second transistors that are nanowire FETs and have the same conductivity type,
- each of the first and second transistors including:
- a nanowire extending along a first direction, the nanowire being a single nanowire or including a plurality of parallelly arranged nanowires;
- first and second pads arranged at both ends of the nanowire in the first direction at a first pitch, having a lower surface below a lower surface of the nanowire, and connected to the nanowire;
- a gate electrode extending along a second direction perpendicular to the first direction, and surrounding a periphery of the nanowire within a predetermined range of the nanowire in the first direction, wherein
- the first and second transistors are connected together in parallel, share the second pads, and arranged adjacent to one another in the first direction.
3 more elements
Dependencies are inferred from the claim text.