Transistor with lightly doped drain (LDD) compensation implant

A method for fabricating a transistor, comprising:

• forming a first semiconductor region;
• forming a second semiconductor region;
• forming a third semiconductor region, the first semiconductor region being formed between and having a different doping type than the second semiconductor region and the third semiconductor region;
• forming a gate dielectric layer above the first semiconductor region;
• forming a non-insulative region above the gate dielectric layer;
• and
• forming a first implant region above the second semiconductor region, the first implant region having a different doping type than the second semiconductor region, wherein the second semiconductor region is configured as a source or a drain of the transistor.

A transistor comprising:

• a first semiconductor region;
• a second semiconductor region;
• a third semiconductor region, the first semiconductor region being between and having a different doping type than the second semiconductor region and the third semiconductor region;
• a gate dielectric layer disposed above the first semiconductor region;
• a non-insulative region disposed above the gate dielectric layer;
• a spacer disposed adjacent to the non-insulative region;
• and
• means for reducing a net doping concentration of a portion of the second semiconductor region, the portion of the second semiconductor region being disposed below a portion of the spacer, wherein the means for reducing the net doping concentration is disposed above the second semiconductor region, the second semiconductor region being configured as a source region or a drain region of the transistor.