TFT substrate, scanning antenna provided with TFT substrate, and method for producing TFT substrate

A TFT substrate including a dielectric substrate and a plurality of antenna unit regions arranged on the dielectric substrate, each of the plurality of antenna unit regions including a TFT and a patch electrode connected to a drain electrode of the TFT, and the TFT substrate further including a transmission and/or reception region including the plurality of antenna unit regions and a non-transmission and/or reception region located on a region other than the transmission and/or reception region, the TFT substrate comprising:

• a gate metal layer supported by the dielectric substrate, and including a gate electrode of the TFT and a gate bus line connected to the gate electrode;
• a gate insulating layer formed on the gate metal layer;
• a source metal layer formed on the gate insulating layer, and including a source electrode of the TFT, the drain electrode, a source bus line connected to the source electrode, and the patch electrode;
• an interlayer insulating layer formed on the source metal layer,
• a conductive layer formed on the interlayer insulating layer;
• and
• a source terminal section and a source gate connection section disposed in the non-transmission and/or reception region,
• wherein the source terminal section includes
• a source terminal lower connection section included in the gate metal layer,
• a first opening formed in the gate insulating layer and at least reaching the source terminal lower connection section,
• a second opening formed in the interlayer insulating layer and overlapping the first opening when viewed from a normal direction of the dielectric substrate, and
• a source terminal upper connection section formed on the interlayer insulating layer and included in the conductive layer,
• the source terminal upper connection section is in contact with the source terminal lower connection section within the first opening,
• the source gate connection section includes
• a source lower connection wiring line included in the gate metal layer and connected to the source terminal lower connection section,
• a third opening formed in the gate insulating layer and at least reaching the source lower connection wiring line,
• a source bus connection section included in the source metal layer and connected to the source bus line,
• a fourth opening formed in the interlayer insulating layer and overlapping the third opening when viewed from the normal direction of the dielectric substrate,
• a fifth opening formed in the interlayer insulating layer and at least reaching the source bus connection section, and
• a source upper connection section formed on the interlayer insulating layer and included in the conductive layer, and
• the source upper connection section is in contact with the source lower connection wiring line within the third opening, and in contact with the source bus connection section within the fifth opening.