Magnetoresistance effect element, magnetic sensor and spin transistor

A magnetoresistance effect element comprising:

• a semiconductor layer;
• and
• a first ferromagnetic layer and a second ferromagnetic layer provided on an upper surface of the semiconductor layer to be spaced apart from each other in a first direction,
• wherein the semiconductor layer has a first region, a second region and a third region each of which includes a part of the upper surface of the semiconductor layer and a part of a lower surface of the semiconductor layer and contains the same semiconductor material as a base material,
• the first ferromagnetic layer is provided on the first region, the second ferromagnetic layer is provided on the second region,
• the third region is sandwiched between the first region and the second region in the first direction,
• the third region has p-type conductivity,
• crystal orientations of the semiconductor material in the first direction are substantially the same in the first region, the second region, and the third region, and
• an interatomic distance of the third region in the crystal orientation of the semiconductor material in the first direction in an upper surface neighboring region including the upper surface is smaller than an interatomic distance of the third region in the crystal orientation of the semiconductor material in the first direction in a lower surface neighboring region including the lower surface.

A spin transistor comprising:

• a magnetoresistance effect element including
• a semiconductor layer, and
• a first ferromagnetic layer and a second ferromagnetic layer provided on an upper surface of the semiconductor layer to be spaced apart from each other in a first direction,
• wherein the semiconductor layer has a first region, a second region and a third region each of which includes a part of the upper surface of the semiconductor layer and a part of a lower surface of the semiconductor layer and contains the same semiconductor material as a base material,
• the first ferromagnetic layer is provided on the first region, the second ferromagnetic layer is provided on the second region,
• the third region is sandwiched between the first region and the second region in the first direction,
• crystal orientations of the semiconductor material in the first direction are substantially the same in the first region, the second region, and the third region, and
• an interatomic distance of the third region in the crystal orientation of the semiconductor material in the first direction in an upper surface neighboring region including the upper surface is larger than an interatomic distance of the third region in the crystal orientation of the semiconductor material in the first direction in a lower surface neighboring region including the lower surface;
• an insulating layer provided on the third region;
• and
• an electrode provided on the third region with the insulating layer therebetween and provided to be spaced apart from the first ferromagnetic layer and the second ferromagnetic layer,
• wherein the first region and the second region have n-type conductivity,
• the electrode serves as a gate electrode, one of the first ferromagnetic layer and the second ferromagnetic layer serves as a source electrode, and the other one of the first ferromagnetic layer and the second ferromagnetic layer serves as a drain electrode,
• the third region has p-type conductivity when no voltage is applied to the gate electrode, and
• the gate electrode is configured to be capable of applying a voltage so that an inversion layer having n-type conductivity is formed in at least a part of the upper surface neighboring region of the third region.

A spin transistor comprising:

• a magnetoresistance effect element including
• a semiconductor layer, and
• a first ferromagnetic layer and a second ferromagnetic layer provided on an upper surface of the semiconductor layer to be spaced apart from each other in a first direction,
• wherein the semiconductor layer has a first region, a second region and a third region each of which includes a part of the upper surface of the semiconductor layer and a part of a lower surface of the semiconductor layer and contains the same semiconductor material as a base material,
• the first ferromagnetic layer is provided on the first region, the second ferromagnetic layer is provided on the second region,
• the third region is sandwiched between the first region and the second region in the first direction,
• crystal orientations of the semiconductor material in the first direction are substantially the same in the first region, the second region, and the third region, and
• an interatomic distance of the third region in the crystal orientation of the semiconductor material in the first direction in an upper surface neighboring region including the upper surface is smaller than an interatomic distance of the third region in the crystal orientation of the semiconductor material in the first direction in a lower surface neighboring region including the lower surface;
• an insulating layer provided on the third region;
• and
• an electrode provided on the third region with the insulating layer therebetween and provided to be spaced apart from the first ferromagnetic layer and the second ferromagnetic layer,
• wherein the first region and the second region have p-type conductivity,
• the electrode serves as a gate electrode, one of the first ferromagnetic layer and the second ferromagnetic layer serves as a source electrode, and the other one of the first ferromagnetic layer and the second ferromagnetic layer serves as a drain electrode,
• the third region has n-type conductivity when no voltage is applied to the gate electrode, and
• the gate electrode is configured to be capable of applying a voltage so that an inversion layer having p-type conductivity is formed in at least a part of the upper surface neighboring region of the third region.