Reduction of fin loss in the formation of FinFETs
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChi On Chui, Yee-Chia Yeo
Life of this patent
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Abstract
A method includes forming a dummy gate stack on a top surface and a sidewall of a middle portion of a semiconductor fin, and forming a spacer layer. The spacer layer includes a first portion on a sidewall of the dummy gate stack, and a second portion on a top surface and a sidewall of a portion of the semiconductor fin. The method further includes performing an implantation on the spacer layer. After the implantation, an anneal is performed. After the anneal, the second portion of the spacer layer is etched, wherein the first portion of the spacer layer remains after the etching. A source/drain region is formed on a side of the semiconductor fin.
Claims20
A method comprising:
- forming a spacer layer comprising:
- a top portion on a topmost surface of a gate stack;
- and
- a sidewall portion on a sidewall of the gate stack, the sidewall portion being a continuous material with the top portion;
- implanting dopants into the top portion of the spacer layer, wherein after the implanting the top portion of the spacer layer has a higher concentration of the dopants than the sidewall portion of the spacer layer;
- and
- after the implanting, performing an isotropic etch process on the spacer layer using an etching chemical, with both of the top portion and the sidewall portion of the spacer layer being exposed to the etching chemical, wherein the top portion is removed by the etching chemical, and the sidewall portion of the spacer layer remains after the isotropic etch process.
A method comprising:
- forming a fin in a semiconductor substrate;
- forming a dummy gate structure over the fin, the dummy gate structure comprising a mask layer;
- depositing a gate spacer layer over an upper surface of the fin, sidewalls of the fin, an upper surface of the dummy gate structure, and sidewalls of the dummy gate structure;
- implanting the gate spacer layer with dopants, the dopants extending into an entirety of a thickness of the gate spacer layer over the upper surface of the fin, over the sidewalls of the fin, and over the upper surface of the dummy gate structure;
- etching to remove the gate spacer layer over the upper surface of the fin, over the sidewalls of the fin, and over the upper surface of the dummy gate structure, wherein after the etching a remaining portion of the gate spacer layer remains over the sidewalls of the dummy gate structure;
- and
- removing the dummy gate structure.
A method comprising:
- forming a dummy gate structure over a substrate, the dummy gate structure having an upper portion and a lower portion, the lower portion being more proximal to the substrate than the upper portion, the dummy gate structure interposing a first semiconductor region and a second semiconductor region, each of the first semiconductor region and the second semiconductor region comprising a top portion and a bottom portion, the bottom portion being more proximal to the substrate than the top portion;
- depositing a gate spacer layer over the dummy gate structure, the first semiconductor region, and the second semiconductor region, the gate spacer layer comprising a topmost portion above the dummy gate structure and a sidewall portion along sidewalls of the dummy gate structure;
- implanting first dopants into the gate spacer layer at a first angle and second dopants into the gate spacer layer at a second angle, the first angle and the second angle forming a vertical plane, the vertical plane being parallel to a sidewall of the dummy gate structure, the topmost portion and the sidewall portion resulting in different etch selectivities;
- and
- after implanting the first dopants, etching the topmost portion of the gate spacer layer.
Dependencies are inferred from the claim text.