FinFET device with a reduced width
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKa-Hing Fung, Chen-Yu Hsieh, Che-Yuan Hsu, Ming-Yuan Wu, Hsu-Chieh Cheng
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKa-Hing Fung, Chen-Yu Hsieh, Che-Yuan Hsu, Ming-Yuan Wu, Hsu-Chieh Cheng
Estimating the term…
A method includes forming a fin structure on a substrate, forming a dummy gate structure wrapped around the fin structure, depositing an Interlayer Dielectric (ILD) layer over the fin structure, removing the dummy gate structure to expose a portion of the fin structure, and performing an etching process on the portion of the fin structure to reduce a width of the portion of the fin structure.
A method comprising:
A method comprising:
A method for forming a semiconductor device comprising:
Dependencies are inferred from the claim text.
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Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
Of fin field-effect transistors [FinFET]: by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins
Insulated-gate field-effect transistors [IGFET]: fin field-effect transistors [FinFET]
Fin field-effect transistors [FinFET]: having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates
About 10 years 6 months of term left · ends 28 Apr 2037 (estimated)
In the semiconductor integrated circuit (IC) industry, technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of IC processing and manufacturing.
One type of semiconductor device that can be fabricated is a Fin Field Effect Transistor (FinFET). In a FinFET, a fin-shaped semiconductor structure is formed on a substrate. A gate device that wraps around the fin structure can then be formed. Additionally, active regions such as source/drain regions are then formed within the fin structure adjacent the gate structure. The gate device and adjacent source/drain regions thus form a transistor with the channel extending through the fin structure underneath the gate. It is desirable that the fin structure has characteristics that provide it with sufficient mechanical strength as well as good carrier mobility.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
FIGS. 1A, 1B, 1C, 1D, 1E, and 1F are diagrams showing an illustrative process for forming a FinFET device with a reduced width, according to one example of principles described herein.
FIG. 2 is a diagram showing various characteristics of FinFET device with a reduced width, according to one example of principles described herein.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
As described above, it is desirable that the fin structure has characteristics that provide it with sufficient mechanical strength as well as good carrier mobility. In general, a smaller fin width may be subject to more structural weakness, and may thus be prone to breaking, deforming, or collapsing. However, a smaller fin width also provides a shorter channel. A shorter channel can lead to improved device performance. Accordingly, it is desirable to have a fin structure that provides a short channel but has sufficient width to provide the desired structural support.