Semiconductor device with interconnect to source/drain

A method of manufacturing a semiconductor device, comprising:

• providing an SOI substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on said semiconductor bulk substrate and a semiconductor layer formed on said buried insulation layer;
• forming a shallow trench isolation in said SOI substrate;
• forming a FET in and over said SOI substrate;
• forming a contact to a source or drain region of said FET, said source or drain region being positioned adjacent to said shallow trench isolation;
• wherein forming said shallow trench isolation comprises (a) forming a trench in said SOI substrate and extending into said semiconductor bulk substrate, (b) filling a lower portion of said trench with a first dielectric layer, (c) forming a spacer layer over said first dielectric layer and over sidewalls of said trench, said spacer layer having a material different from a material of said first dielectric layer, wherein an uppermost surface of said spacer layer does not extend above an uppermost surface of said buried insulation layer, and (d) forming a second dielectric layer over said spacer layer, said second dielectric layer having a material different from said material of said spacer layer;
• and
• forming a liner on sidewalls of said trench before forming said first and second dielectric layers and forming said spacer layer, wherein said liner is made of a material different from said material of said first and second dielectric layers and said spacer layer.

A method of manufacturing a semiconductor device, comprising:

• providing an SOI substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on said semiconductor bulk substrate and a semiconductor layer formed on said buried insulation layer;
• forming a shallow trench isolation in said SOI substrate;
• forming a FET in and over said SOI substrate;
• and
• forming a contact to a source or drain region of said FET, said source or drain region being positioned adjacent to said shallow trench isolation;
• wherein forming said shallow trench isolation comprises:
• forming a trench in said SOI substrate and extending into said semiconductor bulk substrate;
• filling a lower portion of said trench with a first dielectric layer, said first dielectric layer comprising a flowable material;
• forming a second dielectric layer over said first dielectric layer, said second dielectric layer having a material different from a material of said first dielectric layer;
• recessing the second dielectric layer to define an uppermost surface of said second dielectric layer that does not extend above an uppermost surface of said buried insulation layer;
• and
• forming a third dielectric layer over said second dielectric layer, said third dielectric layer having a material different from said material of said second dielectric layer.

A method of manufacturing a semiconductor device, comprising:

• providing an SOI substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on said semiconductor bulk substrate and a semiconductor layer formed on said buried insulation layer;
• forming a shallow trench isolation in said SOI substrate;
• forming a FET in and over said SOI substrate;
• forming a contact to a source or drain region of said FET, said source or drain region being positioned adjacent to said shallow trench isolation;
• wherein forming said shallow trench isolation comprises (a) forming a trench in said SOI substrate and extending into said semiconductor bulk substrate, (b) filling a lower portion of said trench with a first dielectric layer, (c) forming a second dielectric layer over said first dielectric layer, said second dielectric layer having a material different from a material of said first dielectric layer, wherein an uppermost surface of said second dielectric layer does not extend above an uppermost surface of said buried insulation layer, and (d) forming a third dielectric layer over said second dielectric layer, said third dielectric layer having a material different from said material of said second dielectric layer;
• and
• forming at least one oxide layer between substantially vertically oriented surfaces of said second dielectric layer and substantially vertically oriented surfaces of at least one semiconductor material of said SOI substrate.

A method of manufacturing a semiconductor device, comprising:

• providing an SOI substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on said semiconductor bulk substrate and a semiconductor layer formed on said buried insulation layer;
• forming a shallow trench isolation in said SOI substrate;
• forming a FET in and over said SOI substrate;
• and
• forming a contact to a source or drain region of said FET, said source or drain region being positioned adjacent to said shallow trench isolation;
• wherein forming said shallow trench isolation comprises (a) forming a trench in said SOI substrate and extending into said semiconductor bulk substrate, (b) filling a lower portion of said trench with a first dielectric layer, (c) forming a spacer layer over said first dielectric layer and over sidewalls of said trench, said spacer layer having a material different from a material of said first dielectric layer, wherein an uppermost surface of said spacer layer does not extend above an uppermost surface of said buried insulation layer, and (d) forming a second dielectric layer over said spacer layer, said second dielectric layer having a material different from said material of said spacer layer and wherein said spacer layer comprises sidewall spacers, and said second dielectric layer directly mechanically contacts said first dielectric layer between said sidewall spacers.