Vertical field-effect-transistors having a silicon oxide layer with controlled thickness

An integrated circuit comprising:

• at least one vertical field-effect transistor, the vertical field-effect transistor comprising at least:
• a substrate;
• a bottom source/drain region;
• at least one fin structure formed in contact with the bottom source/drain region;
• a bottom spacer layer having a substantially uniform thickness with a thickness variation of less than 3 nm, wherein the bottom spacer layer contacts a sidewall of the at least one fin structure;
• a gate structure in contact with the bottom spacer layer and the at least one fin structure;
• and
• a top spacer layer formed in contact with the gate structure and the at least one fin structure.

A vertical field-effect transistor comprising at least:

• a substrate;
• a bottom source/drain region;
• at least one fin structure formed in contact with the bottom source/drain region;
• a polymer brush based bottom spacer layer having a substantially uniform thickness with a thickness variation of less than 3 nm, wherein the thickness of the polymer brush based bottom spacer layer is related to a molecular weight of a polymer brush from which the polymer brush based bottom spacer layer was formed, and wherein the polymer brush based bottom spacer layer contacts a sidewall of the at least one fin structure;
• and
• a gate structure in contact with the polymer brush based bottom spacer layer and the at least one fin structure.