Fin field effect transistor devices with robust gate isolation

A method of forming a complementary metal oxide semiconductor (CMOS) device, comprising:

• forming a plurality of vertical fins on a substrate;
• forming a bottom isolation layer on the substrate between the vertical fins;
• forming at least two dummy gates across the plurality of vertical fins, wherein the dummy gate are not made of a conductor or semiconductor material;
• forming sidewall spacers on each of the at least two dummy gates;
• forming a masking block on portions of a central portion of one of the at least two dummy gates;
• removing the portions of the at least two dummy gates not covered by the masking block, wherein the portion of the one dummy gate covered by the masking block forms a dummy gate plug between the sidewall spacers;
• forming a gate dielectric layer on the exposed surfaces of the plurality of vertical fins, bottom isolation layer, and dummy gate plug;
• and
• forming a conductive gate layer on the gate dielectric layer, wherein the dummy gate plug physically separates two active gate structures.

A complementary metal oxide semiconductor (CMOS) device, comprising:

• an insulating dummy gate plug between a pair of adjacent vertical fins on a substrate;
• a first active gate structure on one of the pair of vertical fins;
• a second active gate on another one of the pair of vertical fins, wherein the insulating dummy gate plug separates the first active gate structure from the second active gate structure;
• and
• a third active gate structure that is across the pair of adjacent vertical fins.