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US 10,707,319 B2Granted
Gate electrode having a capping layer
AssigneeIntel Corporation
InventorsGilbert Dewey, Mark L. Doczy, Suman Datta, Justin K. Brask, Matthew V. Metz
Life of this patent
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Abstract
A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed. The method includes depositing a dielectric layer on a substrate, followed by deposition of a capping layer in-situ over the dielectric layer prior to any high temperature processing.
Claims20
An integrated circuit structure, comprising:
- a semiconductor body;
- a gate stack over the semiconductor body, the gate stack comprising:
- a gate dielectric layer, the gate dielectric layer comprising hafnium, oxygen and silicon;
- a barrier layer on the gate dielectric layer, the barrier layer comprising titanium and nitrogen and silicon;
- and
- a gate electrode above the barrier layer, the gate electrode comprising aluminum and titanium;
- a first source or drain region in the semiconductor body at a first side of the gate stack;
- and
- a second source or drain region in the semiconductor body at a second side of the gate stack, the second side opposite the first side.
6 more elements
A method of fabricating an integrated circuit structure, the method comprising:
- forming a gate stack over a semiconductor body, forming the gate stack comprising:
- forming a gate dielectric layer, the gate dielectric layer comprising hafnium, oxygen and silicon;
- forming a barrier layer on the gate dielectric layer, the barrier layer comprising titanium and nitrogen;
- forming a layer on the barrier layer, the layer comprising silicon;
- removing the layer comprising silicon;
- and
- forming a gate electrode above the barrier layer, the gate electrode comprising aluminum and titanium;
- forming a first source or drain region in the semiconductor body at a first side of the gate stack;
- and
- forming a second source or drain region in the semiconductor body at a second side of the gate stack, the second side opposite the first side.
7 more elements
Dependencies are inferred from the claim text.