Vertically stacked nFET and pFET with dual work function

A method of forming a semiconductor structure, the method comprising:

• forming a vertical stack of a first nanosheet stack of alternating nanosheets of a sacrificial SiGe nanosheet and a Si channel material nanosheet, and a second nanosheet stack of alternating nanosheets of a sacrificial SiGe nanosheet and a Si channel material nanosheet, wherein the vertical stack is present above a semiconductor substrate and beneath a sacrificial gate structure and a dielectric spacer;
• recessing each sacrificial SiGe nanosheet of the first and second nanosheet stacks;
• removing the sacrificial gate structure and each recessed sacrificial SiGe nanosheet of the first and second nanosheet stacks to suspend each Si channel material nanosheet and to provide a gate cavity;
• forming a gate dielectric material in the gate cavity and on physically exposed surfaces of each suspended Si channel material nanosheet;
• forming a p-type work function metal on the gate dielectric material;
• removing the p-type work function metal from the gate cavity present below and above each suspended Si channel material nanosheet of the second nanosheet stack;
• and
• forming an n-type work function metal in the gate cavity present between and above each suspended Si channel material nanosheet of the second nanosheet stack.