Method, apparatus, and system for improving scaling of isolation structures for gate, source, and/or drain contacts

A method, comprising:

• providing a semiconductor substrate;
• providing an isolation layer disposed on the semiconductor substrate;
• forming a first active region and a second active region disposed at least partially above the isolation layer, wherein the first active region and the second active region each comprise a long axis and a short axis, wherein the long axes of the first and second active regions are substantially parallel and extend in a first direction;
• forming a first gate structure and a second gate structure disposed on the isolation layer, the first active region, and the second active region, wherein the first gate structure and the second gate structure each comprise a long axis and a short axis, wherein the long axes of the first and second gate structures are substantially parallel and extend in a second direction, wherein the second direction is substantially perpendicular to the first direction;
• forming a high-κ material on the isolation layer, the first active region, the second active region, the first gate structure, and the second gate structure, such that a rectangular portion of the isolation layer between the first active region and the second active region, and between and in contact with the first gate structure and the second gate structure, remains exposed;
• forming an isolation pillar material on the rectangular portion of the isolation layer, wherein the isolation pillar material has a rectangular shape in a sectional view taken across the first direction and lower portions of two opposed sides of the isolation pillar material are in contact with the high-κ material;
• and
• trimming upper portions of the two opposed sides of the isolation pillar material, wherein the upper portions are above the lower portions, to yield an isolation pillar disposed on the isolation layer, between the first and second active regions, and between and in contact with the first and second gate structures, wherein the isolation pillar has an inverted-T shape in a sectional view taken across the first direction.

A system, comprising:

• a semiconductor device processing system to manufacture a semiconductor device;
• and
• a processing controller operatively coupled to said semiconductor device processing system, said processing controller configured to control an operation of the semiconductor device processing system;
• wherein the semiconductor device processing system is adapted to:
• provide a semiconductor substrate;
• provide an isolation layer disposed on the semiconductor substrate;
• form a first active region and a second active region disposed at least partially above the isolation layer, wherein the first active region and the second active region each comprise a long axis and a short axis, wherein the long axes of the first and second active regions are substantially parallel and extend in a first direction;
• form a first gate structure and a second gate structure disposed on the isolation layer, the first active region, and the second active region, wherein the first gate structure and the second gate structure each comprise a long axis and a short axis, wherein the long axes of the first and second gate structures are substantially parallel and extend in a second direction, wherein the second direction is substantially perpendicular to the first direction;
• and
• form an isolation structure disposed on the isolation layer, between the first and second active regions, and between and in contact with the first and second gate structures, wherein the isolation structure has an inverted-T shape in a sectional view taken across the first direction.