High voltage galvanic isolation device

An integrated circuit, comprising:

• a substrate;
• a capacitor having:
• a lower conductive plate above the substrate;
• a first dielectric layer above the lower conductive plate;
• a second dielectric layer including:
• a first sub-layer above the first dielectric layer and contiguously coextending with the first dielectric layer;
• and
• a second sub-layer on the first sub-layer, the second sub-layer segregated into a first portion co-extending with the lower conductive plate, and a second portion spaced apart from the first portion;
• and
• an upper conductive plate above and within the first portion the second sub-layer.

A method of fabricating an integrated circuit, comprising:

• forming a lower conductive plate above a substrate;
• forming a first dielectric layer above the lower conductive plate;
• forming a second dielectric layer including forming a first sub-layer above the first dielectric layer and forming a second sub-layer above the first sub-layer;
• and
• forming an isolation break by etching through the second sub-layer and terminating the etch before etching through the first sub-layer, the isolation break dividing the second sub-layer into:
• a first portion co-extending with the lower conductive plate;
• and
• a second portion;
• and
• forming an upper conductive plate above the second sub-layer, the upper conductive plate being circumscribed by the isolation break.