Semiconductor memory device having vertical supporter penetrating the gate stack structure and through dielectric pattern
AssigneeSamsung Electronics Co., Ltd.
InventorsKyeong Jin Park, Seo-Goo Kang, Kwonsoon Jo, Kohji Kanamori
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Abstract
Disclosed is a semiconductor memory device comprising a peripheral circuit structure on a first substrate, a second substrate on the peripheral circuit structure, a stack structure on the second substrate and comprising a plurality of gate electrodes, a through dielectric pattern penetrating the stack structure and the second substrate, and a vertical supporter on a top surface of the second substrate and vertically extending from the top surface of the second substrate and penetrating the stack structure and the through dielectric pattern.
Claims20
A semiconductor memory device, comprising:
- a peripheral circuit structure on a first substrate;
- a second substrate on the peripheral circuit structure;
- a stack structure on the second substrate and comprising a plurality of gate electrodes;
- a through dielectric pattern penetrating the stack structure and the second substrate, wherein the through dielectric pattern is disposed on a sloped sidewall of the stack structure;
- and
- a vertical supporter on a top surface of the second substrate and vertically extending from the top surface of the second substrate,
- wherein the vertical supporter penetrates the through dielectric pattern and further penetrates the stack structure from the sloped sidewall thereof to the top surface of the second substrate.
A semiconductor memory device, comprising:
- a peripheral circuit structure on a first substrate;
- an interlayer dielectric layer covering the peripheral circuit structure;
- a second substrate on the peripheral circuit structure and having a recess part exposing a portion of the interlayer dielectric layer covering the peripheral circuit structure;
- a stack structure on the second substrate and comprising a plurality of gate electrodes;
- a through dielectric pattern filling the recess part and penetrating the stack structure,
- the through dielectric pattern comprising:
- a first segment vertically overlapping the recess part;
- and
- a second segment surrounding the first segment and disposed on a sidewall of the stack structure;
- and
- a vertical supporter penetrating the second segment of the through dielectric pattern and the stack structure.
A semiconductor memory device, comprising:
- a peripheral circuit structure on a first substrate;
- a second substrate on the peripheral circuit structure and having a recess part exposing the peripheral circuit structure;
- a stack structure on a top surface of the second substrate and comprising a plurality of gate electrodes;
- a through dielectric pattern on the recess part and covering a sidewall of the stack structure;
- and
- a vertical supporter on a top surface of the second substrate and vertically extending from the top surface of the second substrate and penetrating the through dielectric pattern and the stack structure,
- wherein the vertical supporter comprises a semiconductor material.
Dependencies are inferred from the claim text.