Semiconductor device including stack structure and trenches

#This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2017-0106033, filed on Aug. 22, 2017, in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated by reference herein in its entirety.

#Exemplary embodiments of the present inventive concept relate to a semiconductor device, and more particularly to a semiconductor device including a stack structure and trenches.

#A degree of integration of semiconductor devices may be increased by the lighting, thinning, and shortening of electronic devices. As an example, a technique using a stack structure in which insulating layers and electrode layers are alternately and repeatedly stacked on a substrate has been attempted. A plurality of cell blocks may be defined by a plurality of trenches which vertically pass through the stack structure and are in parallel. Each of the trenches may have a relatively high aspect ratio. In a semiconductor device including trenches, an outermost trench among the trenches may be vulnerable to various defects caused by mold leaning.

#The above and other objects, features and aspects of the present inventive concept will become more apparent to those of ordinary skill in the art by describing exemplary embodiments thereof in detail with reference to the accompanying drawings, in which:

#FIGS. 1 to 6 are cross-sectional views illustrating a semiconductor device according to an exemplary embodiment of the present inventive concept;

#FIGS. 1 and 8 are each partially enlarged views illustrating a part of FIG. 1;

#FIGS. 1 to 6 are cross-sectional views illustrating a semiconductor device according to an exemplary embodiment of the present inventive concept. FIGS. 7 and 8 are each partially enlarged views illustrating a part of FIG. 1. A semiconductor device according to an exemplary embodiment of the present inventive concept may include a flash memory such as a vertical-NAND (VNAND) or a three dimensional NAND (3D-NAND) memory.

#Referring to FIG. 1, a semiconductor device according to an exemplary embodiment of the present inventive concept may include a cell array region having a main block region MB and a dummy block region DB. The dummy block region DB may be continuous with the main block region MB. The dummy block region DB may be provided at an edge of the cell array region. As an example, a substrate 21 may include the dummy block region DB and the main block region MB.

#The semiconductor device may include insulating layers 25, mold layers 27, a first insulating interlayer 29, pillars 41 and 42, a second insulating interlayer 45, trenches 131, 132, 141, 142, and 143, impurity regions 47, a gate insulating layer 53, gate electrodes G1 to Gn, a spacer 55, source lines 151, 152, 161, 162, and 163, a third insulating interlayer 57, first bit plugs 61, sub-bit lines 63, a fourth insulating interlayer 65, second hit plugs 67, and bit lines 69, which are formed on a substrate 21 having the main block region MB and the dummy block region DB.