FinFET vertical flash memory

A method of forming a semiconductor structure, the method comprising:

• forming a plurality of fin structures on a surface of a first doped semiconductor layer of a first conductivity type, wherein each fin structure of the plurality of fin structures includes from bottom to top, a non-doped semiconductor portion and a second doped semiconductor portion of the first conductivity type;
• forming a first sacrificial spacer surrounding each fin structure;
• patterning the first doped semiconductor layer not protected by the fin structure and the first sacrificial spacer to provide a plurality of first doped semiconductor portions beneath each fin structure;
• removing the first sacrificial gate spacer from each fin structure;
• forming a dielectric material layer between each fin structure and on a topmost surface of each first doped semiconductor portion;
• forming a second sacrificial spacer surrounding each fin structure and located on a topmost surface of the dielectric material layer;
• removing the dielectric material layer to expose a bottom sidewall surface of each non-doped semiconductor portion of each fin structure;
• forming a trapping material on the exposed bottom sidewall surface of each non-doped semiconductor fin portion;
• removing the second sacrificial spacer;
• and
• forming a plurality of function gate structures straddling each fin structure of the plurality of fin structures.