US 10,707,221 B2Granted

Step coverage improvement for memory channel layer in 3D NAND memory

AssigneeYangtze Memory Technologies Co., Ltd.

InventorsEr Wei Wang, Yonggang Yang

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Abstract

Embodiments of an etching method for a material layer of a NAND memory device are disclosed. An example method of chemically etching a material layer on one or more substrates includes mixing an etchant solution within a bath and allowing the etchant solution to reach a quiescent state. After the etchant solution has reached the quiescent state, the method includes loading the one or more substrates into the bath. The one or more substrates includes a plurality of openings having the material layer disposed on an inside surface of the plurality of openings. The method also includes allowing the one or more substrates to remain in the bath for a predetermined time period, such that a thickness of the material layer is reduced by the etchant solution.

Claims20

Dependent claims

A method for forming three-dimensional (3D) NAND memory devices, comprising:

disposing a dielectric layer stack on a substrate;
forming a plurality of NAND strings in the dielectric layer stack, the forming comprising:
disposing a memory layer on inside surfaces of the dielectric layer stack such that one or more openings are surrounded by sidewalk of the memory layer;
mixing an etchant solution within a bath;
allowing the etchant solution to reach a quiescent state;
after the etchant solution has reached the quiescent state, loading the substrate, the dielectric layer stack, and the memory layer into the bath
allowing the substrate, the dielectric layer stack, and the memory layer to remain in the bath for a predetermined time period, such that the etchant solution moves into the one or more openings by capillary action and a thickness of the memory layer is non-uniformly reduced by the etchant solution;
and
disposing a core filling film in the one or more openings after the thickness of the memory layer is reduced;
and
disposing bit lines over the dielectric layer stack, wherein the bit lines are connected to the plurality of NAND strings.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/169,759Filed 24 Oct 2018 · continuation
Priority: 26 Sep 2018
Published: US 2020/0098772 A126 Mar 2020
Granted: 7 Jul 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10D 64/037
Of data-storage electrodes: comprising charge-trapping insulators
H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35
Characterised by the memory core region: with cell select transistors, e.g. NAND