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US 10,707,220 B2Granted
Ferroelectric memory and methods of forming the same
AssigneeMicron Technology, Inc.
InventorsAshonita A. Chavan, Alessandro Calderoni, D. V. Nirmal Ramaswamy
Life of this patent
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Abstract
Ferroelectric memory and methods of forming the same are provided. An example memory cell can include a buried recessed access device (BRAD) formed in a substrate and a ferroelectric capacitor formed on the BRAD.
Claims12
A memory cell, comprising:
- a buried recessed access device (BRAD) formed in a substrate, wherein a gate of the BRAD is formed between a first source/drain region and a second source/drain region corresponding to the BRAD, and wherein the gate is formed below an upper surface of at least one of the first and the second source/drain region;
- a ferroelectric capacitor formed on the BRAD, wherein a bottom electrode of the ferroelectric capacitor is coupled to the first source/drain region, and wherein a top electrode of the ferroelectric capacitor is coupled to the second source/drain region;
- and
- a conductive contact coupled to the top electrode and to the second source/drain region, wherein the conductive contact is not positioned in alignment with the ferroelectric capacitor and an adjacent ferroelectric capacitor of an adjacent memory cell of a same row of memory cells and wherein the conductive contact is formed at least partially on the second source/drain region and at least partially on a dielectric material formed in a substrate corresponding to an isolation region between the same row of memory cells and an adjacent row.
1 more element
A ferroelectric random access memory (FeRAM), comprising:
- a first plurality of ferroelectric capacitors coupled in series between a first conductive line and a second conductive line;
- and
- a second plurality of ferroelectric capacitors coupled in series between the first conductive line and a third conductive line;
- wherein each of the first and second plurality of ferroelectric capacitors are coupled to a respective buried recessed access device (BRAD) having a gate electrode formed beneath the corresponding ferroelectric capacitor;
- wherein each of the first plurality of ferroelectric capacitors are formed in a container and include:
- a bottom electrode formed on sidewalls of the container and on a bottom electrode contact;
- a ferroelectric material formed in the container and on sidewalls of the bottom electrode;
- a top electrode formed in the container and on sidewalls of the ferroelectric material, the top electrode coupled to a source/drain region of the corresponding BRAD via a conductive pillar, wherein a distance from the conductive pillar to a first side of a ferroelectric capacitor of the first plurality is different than a distance from the conductive pillar to a second side of the ferroelectric capacitor of the first plurality;
- and
- wherein the conductive pillar is not positioned in alignment with the first plurality and second plurality of ferroelectric capacitors of a same row of ferroelectric capacitors and wherein at least a portion of the conductive pillar is formed at least partially on an isolation region formed in a substrate separating BRADs corresponding to the first plurality of ferroelectric capacitors and BRADs corresponding to the second plurality of ferroelectric capacitors.
7 more elements
Dependencies are inferred from the claim text.