US 10,707,219 B2Granted

Semiconductor integrated circuit

AssigneeKabushiki Kaisha Toshiba

InventorsYinghao Ho, Masato Oda, Shinichi Yasuda

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Abstract

A semiconductor integrated circuit of an embodiment includes: first to fifth wiring lines; a first OTP memory element including a first and second terminals connected to the first and second wiring lines; a first p-channel transistor including a source and drain terminals connected to the first and third wiring line, and a gate terminal receiving a first control signal; a first n-channel transistor including a source and drain terminals connected to the first and fourth wiring lines, and a gate terminal receiving a second control signal; a second p-channel transistor including a source and drain terminals connected to the second and third wiring lines, and a gate terminal receiving a third control signal; and a second n-channel transistor including a source and drain terminals connected to the second and fifth wiring lines, and a gate terminal receiving a fourth control signal.

Claims14

Dependent claims

A semiconductor integrated circuit comprising:

first to fifth wiring lines;
a first OTP memory element including a first terminal connected to the first wiring line and a second terminal connected to the second wiring line;
a first p-channel transistor including a source terminal and a drain terminal, one of which is connected to the first wiring line and the other of which is connected to the third wiring line, and a gate terminal, which receives a first control signal;
a first n-channel transistor including a source terminal and a drain terminal, one of which is connected to the first wiring line and the other of which is connected to the fourth wiring line, and a gate terminal, which receives a second control signal;
a second p-channel transistor including a source terminal and a drain terminal, one of which is connected to the second wiring line and the other of which is connected to the third wiring line, and a gate terminal, which receives a third control signal;
and
a second n-channel transistor including a source terminal and a drain terminal, one of which is connected to the second wiring line and the other of which is connected to the fifth wiring line, and a gate terminal, which receives a fourth control signal.

4 more elements

A semiconductor integrated circuit comprising:

first to fourth wiring lines;
a first OTP memory element including a first terminal connected to the first wiring line and a second terminal connected to the second wiring line;
a first p-channel transistor including a source terminal and a drain terminal, one of which is connected to the first wiring line and the other of which is connected to the third wiring line, and a gate terminal, which receives a first control signal;
and
a first n-channel transistor including a source terminal and a drain terminal, one of which is connected to the first wiring line and the other of which is connected to the fourth wiring line, and a gate terminal, which receives a second control signal.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/296,780Filed 8 Mar 2019
Priority: JP 2018-17071312 Sep 2018
Published: US 2020/0083235 A112 Mar 2020
Granted: 7 Jul 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H03K 19/20
Logic circuits, i.e. having at least two inputs acting on one output ; Inverting circuits: characterised by logic function, e.g. AND, OR, NOR, NOT…
G11C 17/18
In which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of…
H03K 19/177
Using elementary logic circuits as components: arranged in matrix form
H10B 20/25
Programmable ROM [PROM] devices comprising field-effect components: one-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links