US 10,707,218 B2Granted

Two port SRAM cell using complementary nano-sheet/wire transistor devices

AssigneeGlobalfoundries Inc.

InventorsBipul C. Paul, Ruilong Xie

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Abstract

One illustrative device disclosed herein includes a first pull-up transistor positioned in a first P-type nano-sheet and a first pull-down transistor and a first pass gate transistor positioned in a first N-type nano-sheet. The device further includes a second pull-up transistor positioned in a second P-type nano-sheet and a second pull-down transistor and a second pass gate transistor positioned in a second N-type nano-sheet. The device further includes a read pull-down transistor and a read pass gate transistor positioned in a third N-type nano-sheet. The device also includes a first shared gate structure positioned adjacent the first pull-up transistor and the first pull-down transistor and a second shared gate structure positioned adjacent the second pull-up transistor, the second pull-down transistor and the read pull-down transistor.

Claims20

Dependent claims

A device comprising:

a first stacked nano-sheet device having a first stack comprising a first P-type nano-sheet and a first N-type nano-sheet, a first pull-up transistor positioned in the first P-type nano-sheet, and a first pull-down transistor and a first pass gate transistor positioned in the first N-type nano-sheet;
a second stacked nano-sheet device having a second stack comprising a second P-type nano-sheet and a second N-type nano-sheet, a second pull-up transistor positioned in the second P-type nano-sheet, and a second pull-down transistor and a second pass gate transistor positioned in the second N-type nano-sheet;
a third stacked nano-sheet device having a third stack comprising at least a third N-type nano-sheet, a read pull-down transistor and a read pass gate transistor positioned in the third N-type nano-sheet;
a first shared gate structure positioned adjacent the first pull-up transistor and the first pull-down transistor;
and
a second shared gate structure positioned adjacent the second pull-up transistor, the second pull-down transistor, and the read pull-down transistor.

3 more elements

A method, comprising:

forming a first stacked nano-sheet device having a first stack comprising a first P-type nano-sheet and a first N-type nano-sheet;
forming a first pull-up transistor in the first P-type nano-sheet;
forming a first pull-down transistor and a first pass gate transistor in the first N-type nano-sheet;
forming a second stacked nano-sheet device having a second stack comprising a second P-type nano-sheet and a second N-type nano-sheet;
forming a second pull-up transistor in the second P-type nano-sheet;
forming a second pull-down transistor and a second pass gate transistor in the second N-type nano-sheet;
forming a third stacked nano-sheet device having a third stack comprising at least a third N-type nano-sheet;
forming a read pull-down transistor and a read pass gate transistor in the third N-type nano-sheet;
forming a first shared gate structure adjacent the first pull-up transistor and the first pull-down transistor;
and
forming a second shared gate structure adjacent the second pull-up transistor, the second pull-down transistor, and the read pull-down transistor.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/045,920Filed 26 Jul 2018
Published: US 2020/0035686 A130 Jan 2020
Granted: 7 Jul 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification18 codes

H10B 10/12
Static random access memory [SRAM] devices: comprising a MOSFET load element
H10D 62/121
Nanowire, nanosheet or nanotube semiconductor bodies: oriented parallel to substrates
B82Y 10/00
Nanotechnology for information processing, storage or transmission
G11C 11/412
Forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt…