Methods of forming semiconductor devices, and related semiconductor devices, memory devices, and electronic systems

A memory device, comprising:

• a memory controller;
• a row decoder operably coupled to the memory controller;
• a column decoder operably coupled to the memory controller;
• word lines operably coupled to the row decoder;
• digit lines operably coupled to the column decoder;
• memory cells positioned at intersections of the word lines and the digit lines, the memory cells comprising capacitors and transistors electrically connected to the capacitors;
• cell contact structures laterally between the digit lines;
• nitride structures vertically overlying the digit lines;
• redistribution structures operably coupled to and extending between the cell contact structures and capacitors of the memory cells, the redistribution structures comprising:
• upper portions overlying upper surfaces of the nitride structures;
• and
• lower portions overlying upper surfaces of the cell contact structures;
• a low-K dielectric material laterally between the digit lines and the cell contact structures;
• air gaps laterally between the low-K dielectric material and the cell contact structures, and having upper boundaries below the upper surfaces of the nitride structures;
• and
• a nitride dielectric material laterally between the air gaps and the cell contact structures.

An electronic system, comprising:

• an input device;
• an output device;
• a processor device operably coupled to the input device and the output device;
• and
• a memory device operably coupled to the processor device and comprising a semiconductive device structure comprising:
• laterally alternating semiconductive pillars and digit lines;
• a low-K dielectric material intervening between the digit lines and the semiconductive pillars;
• air gaps intervening between the low-K dielectric material and the semiconductive pillars;
• a nitride dielectric material intervening between the air gaps and the semiconductive pillars;
• nitride dielectric structures vertically overlying the digit lines and having uppermost boundaries vertically above uppermost boundaries of the air gaps;
• and
• conductive redistribution structures electrically connecting the semiconductive pillars to capacitors, upper portions of the conductive redistribution structures vertically overlying the uppermost boundaries of the nitride dielectric structures, and lower portions of the conductive redistribution structures vertically overlying uppermost boundaries of the semiconductive pillars.