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US 10,707,204 B2Granted
Composite semiconductor device
AssigneeSharp Kabushiki Kaisha
InventorSeiichiro Kihara
Life of this patent
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Abstract
A composite semiconductor device with improved response performance and reliability is provided while an increase in wiring area being suppressed. Fingers 1 are arranged in a plurality of rows and a plurality of columns. A signal inputted via a gate terminal (3) is supplied from intermediate regions in a row-wise direction of gate wires (18) connected to gate electrodes (G) of the same row or two adjacent rows of fingers 1 of the fingers 1 and formed along the rows.
Claims4
A composite semiconductor device comprising:
- a semiconductor device including a plurality of normally-off field-effect transistors, a gate terminal, a drain terminal, and a source terminal;
- a normally-on field-effect transistor;
- a second gate terminal;
- a second drain terminal;
- and
- a second source terminal,
- wherein each of the plurality of normally-off field-effect transistors has a gate electrode connected to the gate terminal, a drain electrode connected to the drain terminal, and a source electrode connected to the source terminal,
- the semiconductor device has a first surface on which the gate terminal and either of the drain terminal and the source terminal are formed and a second surface on which the other of the drain terminal and the source terminal is formed, the second surface being a surface opposite to the first surface,
- the second drain terminal is connected to a drain electrode of the normally-on field-effect transistor,
- the second source terminal is connected to a gate electrode of the normally-on field-effect transistor and a source terminal of the semiconductor device,
- the second gate terminal is connected to a gate terminal of the semiconductor device,
- a source electrode of the normally-on field-effect transistor is connected to a drain terminal of the semiconductor device,
- the plurality of normally-off field-effect transistors are arranged in a plurality of rows and a plurality of columns, and
- the semiconductor device includes gate wires connected to the gate electrodes of the same row or two adjacent rows of field-effect transistors of the plurality of normally-off field-effect transistors and formed along the rows,
- the gate terminal is disposed outside a block including the normally-off field-effect transistors arranged in the plurality of rows and the plurality of columns,
- the semiconductor device includes one trunk line connected to intermediate regions in a row-wise direction of the gate wires and formed along a column-wise direction and a connecting line formed along the gate wires and connecting an intermediate region in the column-wise direction of the trunk line with the gate terminal,
- a signal inputted via the gate terminal, the connecting line, and the trunk line is supplied from the intermediate regions in the row-wise direction of the gate wires.
14 more elements
Dependencies are inferred from the claim text.